From 666abcb51ac69161a548055ee41274f2131551ca Mon Sep 17 00:00:00 2001 From: "Y.C. Chen" Date: Wed, 13 Jul 2011 16:20:31 +0800 Subject: xf86-video-ast-0.93.09 --- configure.ac | 2 +- src/ast.h | 3 + src/ast_driver.c | 60 ++- src/ast_mode.c | 10 +- src/ast_vgatool.c | 1491 ++++++++++++++++++++++++++++++++++++++--------------- 5 files changed, 1140 insertions(+), 426 deletions(-) diff --git a/configure.ac b/configure.ac index a573e00..87ba653 100644 --- a/configure.ac +++ b/configure.ac @@ -23,7 +23,7 @@ # Initialize Autoconf AC_PREREQ([2.60]) AC_INIT([xf86-video-ast], - [0.92.02], + [0.93.09], [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], [xf86-video-ast]) AC_CONFIG_SRCDIR([Makefile.am]) diff --git a/src/ast.h b/src/ast.h index 7802b7a..7ceee31 100644 --- a/src/ast.h +++ b/src/ast.h @@ -240,6 +240,9 @@ typedef struct _ASTRec { int clip_right; int clip_bottom; + int mon_h_active; /* Monitor Info. */ + int mon_v_active; + #ifdef AstVideo XF86VideoAdaptorPtr adaptor; Atom xvBrightness, xvContrast, xvColorKey, xvHue, xvSaturation; diff --git a/src/ast_driver.c b/src/ast_driver.c index 4a10e6e..bd3d338 100644 --- a/src/ast_driver.c +++ b/src/ast_driver.c @@ -285,7 +285,7 @@ ASTProbe(DriverPtr drv, int flags) devSections, numDevSections, drv, &usedChips); - xfree(devSections); + free(devSections); if (flags & PROBE_DETECT) { if (numUsed > 0) @@ -322,7 +322,7 @@ ASTProbe(DriverPtr drv, int flags) } /* end of for-loop */ } /* end of if flags */ - xfree(usedChips); + free(usedChips); return foundScreen; } @@ -347,6 +347,7 @@ ASTPreInit(ScrnInfoPtr pScrn, int flags) ClockRangePtr clockRanges; int i; MessageType from; + int maxPitch, maxHeight; /* Suport one adapter only now */ if (pScrn->numEntities != 1) @@ -462,7 +463,7 @@ ASTPreInit(ScrnInfoPtr pScrn, int flags) * and pScrn->entityList should be initialized before */ xf86CollectOptions(pScrn, NULL); - if (!(pAST->Options = xalloc(sizeof(ASTOptions)))) + if (!(pAST->Options = malloc(sizeof(ASTOptions)))) { ASTFreeRec(pScrn); return FALSE; @@ -624,23 +625,37 @@ ASTPreInit(ScrnInfoPtr pScrn, int flags) clockRanges->clockIndex = -1; clockRanges->interlaceAllowed = FALSE; clockRanges->doubleScanAllowed = FALSE; - + /* Add for AST2100, ycchen@061807 */ if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST1180)) - i = xf86ValidateModes(pScrn, pScrn->monitor->Modes, - pScrn->display->modes, clockRanges, - 0, 320, 1920, 8 * pScrn->bitsPerPixel, - 200, 1200, - pScrn->display->virtualX, pScrn->display->virtualY, - pAST->FbMapSize, LOOKUP_BEST_REFRESH); + { + maxPitch = 1920; + maxHeight = 1200; + } else - i = xf86ValidateModes(pScrn, pScrn->monitor->Modes, + { + maxPitch = 1600; + maxHeight = 1200; + } + + i = xf86ValidateModes(pScrn, pScrn->monitor->Modes, pScrn->display->modes, clockRanges, - 0, 320, 1600, 8 * pScrn->bitsPerPixel, - 200, 1200, + 0, 320, maxPitch, 8 * pScrn->bitsPerPixel, + 200, maxHeight, pScrn->display->virtualX, pScrn->display->virtualY, - pAST->FbMapSize, LOOKUP_BEST_REFRESH); + pAST->FbMapSize, LOOKUP_BEST_REFRESH); + /* fixed some monitors can't get propery validate modes using estimated ratio modes */ + if (i < 2) /* validate modes are too few */ + { + i = xf86ValidateModes(pScrn, pScrn->monitor->Modes, + pScrn->display->modes, clockRanges, + 0, 320, maxPitch, 8 * pScrn->bitsPerPixel, + 200, maxHeight, + pAST->mon_h_active, pAST->mon_v_active, + pAST->FbMapSize, LOOKUP_BEST_REFRESH); + } + if (i == -1) { ASTFreeRec(pScrn); return FALSE; @@ -758,6 +773,11 @@ ASTScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv) FBMemBox.x2 = pScrn->displayWidth; FBMemBox.y2 = (AvailFBSize / (pScrn->displayWidth * ((pScrn->bitsPerPixel+1)/8))) - 1; + if (FBMemBox.y2 < 0) + FBMemBox.y2 = 32767; + if (FBMemBox.y2 < pScrn->virtualY) + return FALSE; + if (!xf86InitFBManager(pScreen, &FBMemBox)) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to init memory manager\n"); return FALSE; @@ -1117,7 +1137,7 @@ ASTFreeRec(ScrnInfoPtr pScrn) return; if (!pScrn->driverPrivate) return; - xfree(pScrn->driverPrivate); + free(pScrn->driverPrivate); pScrn->driverPrivate = 0; } @@ -1495,6 +1515,10 @@ ASTDoDDC(ScrnInfoPtr pScrn, int index) } } + + /* save MonInfo to Private */ + pAST->mon_h_active = MonInfo->det_mon[0].section.d_timings.h_active; + pAST->mon_v_active = MonInfo->det_mon[0].section.d_timings.v_active; xf86PrintEDID(MonInfo); xf86SetDDCproperties(pScrn, MonInfo); @@ -2003,7 +2027,7 @@ static XF86VideoAdaptorPtr ASTSetupImageVideo(ScreenPtr pScreen) ASTPortPrivPtr pPriv; - if(!(adapt = xcalloc(1, sizeof(XF86VideoAdaptorRec) + + if(!(adapt = calloc(1, sizeof(XF86VideoAdaptorRec) + sizeof(DevUnion) + sizeof(ASTPortPrivRec)))) return NULL; @@ -2094,7 +2118,7 @@ void ASTInitVideo(ScreenPtr pScreen) } else { - newAdaptors = xalloc((num_adaptors + 1) * sizeof(XF86VideoAdaptorPtr*)); + newAdaptors = malloc((num_adaptors + 1) * sizeof(XF86VideoAdaptorPtr*)); if(newAdaptors) { memcpy(newAdaptors, adaptors, num_adaptors * @@ -2110,7 +2134,7 @@ void ASTInitVideo(ScreenPtr pScreen) xf86XVScreenInit(pScreen, adaptors, num_adaptors); if(newAdaptors) - xfree(newAdaptors); + free(newAdaptors); } #endif /* AstVideo */ diff --git a/src/ast_mode.c b/src/ast_mode.c index f971ff2..b58916f 100644 --- a/src/ast_mode.c +++ b/src/ast_mode.c @@ -51,9 +51,15 @@ /* H/W cursor support */ #include "xf86Cursor.h" +/* usleep() */ +#include + /* Driver specific headers */ #include "ast.h" +/* external reference fucntion */ +extern Bool bInitAST1180(ScrnInfoPtr pScrn); + VBIOS_STDTABLE_STRUCT StdTable[] = { /* MD_2_3_400 */ { @@ -795,8 +801,8 @@ void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAMod /* Set Threshold */ if (pAST->jChipType == AST2300) { - SetIndexReg(CRTC_PORT,0xA7, 0x6F); - SetIndexReg(CRTC_PORT,0xA6, 0x3F); + SetIndexReg(CRTC_PORT,0xA7, 0x78); + SetIndexReg(CRTC_PORT,0xA6, 0x60); } else if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) ) { diff --git a/src/ast_vgatool.c b/src/ast_vgatool.c index 674b3da..4a90dd4 100644 --- a/src/ast_vgatool.c +++ b/src/ast_vgatool.c @@ -51,6 +51,9 @@ /* H/W cursor support */ #include "xf86Cursor.h" +/* usleep() */ +#include + /* Driver specific headers */ #include "ast.h" @@ -720,6 +723,185 @@ void vSetDefExtReg(ScrnInfoPtr pScrn) } +__inline ULONG MIndwm(UCHAR *mmiobase, ULONG r) +{ + *(ULONG *) (mmiobase + 0xF004) = r & 0xFFFF0000; + *(ULONG *) (mmiobase + 0xF000) = 0x1; + + return ( *(volatile ULONG *) (mmiobase + 0x10000 + (r & 0x0000FFFF)) ); + +} + +__inline void MOutdwm(UCHAR *mmiobase, ULONG r, ULONG v) +{ + + *(ULONG *) (mmiobase + 0xF004) = r & 0xFFFF0000; + *(ULONG *) (mmiobase + 0xF000) = 0x1; + + *(volatile ULONG *) (mmiobase + 0x10000 + (r & 0x0000FFFF)) = v; +} + +/* + * AST2100/2150 DLL CBR Setting + */ +#define CBR_SIZE_AST2150 ((16 << 10) - 1) +#define CBR_PASSNUM_AST2150 5 +#define CBR_THRESHOLD_AST2150 10 +#define CBR_THRESHOLD2_AST2150 10 +#define TIMEOUT_AST2150 5000000 + +#define CBR_PATNUM_AST2150 8 + +ULONG pattern_AST2150[14] ={ +0xFF00FF00, +0xCC33CC33, +0xAA55AA55, +0xFFFE0001, +0x683501FE, +0x0F1929B0, +0x2D0B4346, +0x60767F02, +0x6FBE36A6, +0x3A253035, +0x3019686D, +0x41C6167E, +0x620152BF, +0x20F050E0}; + +typedef struct _AST2150DRAMParam { + UCHAR *pjMMIOVirtualAddress; +} AST2150DRAMParam, *PAST2150DRAMParam; + +ULONG MMCTestBurst2_AST2150(PAST2150DRAMParam param, ULONG datagen) +{ + ULONG data, timeout; + UCHAR *mmiobase; + + mmiobase = param->pjMMIOVirtualAddress; + + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000001 | (datagen << 3)); + timeout = 0; + do{ + data = MIndwm(mmiobase, 0x1E6E0070) & 0x40; + if(++timeout > TIMEOUT_AST2150){ + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(-1); + } + }while(!data); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000003 | (datagen << 3)); + timeout = 0; + do{ + data = MIndwm(mmiobase, 0x1E6E0070) & 0x40; + if(++timeout > TIMEOUT_AST2150){ + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(-1); + } + }while(!data); + data = (MIndwm(mmiobase, 0x1E6E0070) & 0x80) >> 7; + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(data); +} + +ULONG MMCTestSingle2_AST2150(PAST2150DRAMParam param, ULONG datagen) +{ + ULONG data, timeout; + UCHAR *mmiobase; + + mmiobase = param->pjMMIOVirtualAddress; + + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000005 | (datagen << 3)); + timeout = 0; + do{ + data = MIndwm(mmiobase, 0x1E6E0070) & 0x40; + if(++timeout > TIMEOUT_AST2150){ + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(-1); + } + }while(!data); + data = (MIndwm(mmiobase, 0x1E6E0070) & 0x80) >> 7; + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(data); +} + +int CBRTest_AST2150(PAST2150DRAMParam param) +{ + UCHAR *mmiobase; + + mmiobase = param->pjMMIOVirtualAddress; + + if(MMCTestBurst2_AST2150(param, 0) ) return(0); + if(MMCTestBurst2_AST2150(param, 1) ) return(0); + if(MMCTestBurst2_AST2150(param, 2) ) return(0); + if(MMCTestBurst2_AST2150(param, 3) ) return(0); + if(MMCTestBurst2_AST2150(param, 4) ) return(0); + if(MMCTestBurst2_AST2150(param, 5) ) return(0); + if(MMCTestBurst2_AST2150(param, 6) ) return(0); + if(MMCTestBurst2_AST2150(param, 7) ) return(0); + return(1); + +} + +int CBRScan_AST2150(PAST2150DRAMParam param, int busw) +{ + ULONG patcnt, loop; + UCHAR *mmiobase; + + mmiobase = param->pjMMIOVirtualAddress; + + for(patcnt = 0;patcnt < CBR_PATNUM_AST2150;patcnt++){ + MOutdwm(mmiobase, 0x1E6E007C, pattern_AST2150[patcnt]); + for(loop = 0;loop < CBR_PASSNUM_AST2150;loop++){ + if(CBRTest_AST2150(param)){ + break; + } + } + if(loop == CBR_PASSNUM_AST2150){ + return(0); + } + } + return(1); + +} + +void CBRDLLI_AST2150(PAST2150DRAMParam param, int busw) +{ + ULONG dllmin[4], dllmax[4], dlli, data, passcnt; + UCHAR *mmiobase; + + mmiobase = param->pjMMIOVirtualAddress; + + CBR_START: + dllmin[0] = dllmin[1] = dllmin[2] = dllmin[3] = 0xff; + dllmax[0] = dllmax[1] = dllmax[2] = dllmax[3] = 0x0; + passcnt = 0; + MOutdwm(mmiobase, 0x1E6E0074, CBR_SIZE_AST2150); + for(dlli = 0;dlli < 100;dlli++){ + MOutdwm(mmiobase, 0x1E6E0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); + data = CBRScan_AST2150(param, busw); + if(data != 0){ + if(data & 0x1){ + if(dllmin[0] > dlli){ + dllmin[0] = dlli; + } + if(dllmax[0] < dlli){ + dllmax[0] = dlli; + } + } + passcnt++; + }else if(passcnt >= CBR_THRESHOLD_AST2150){ + break; + } + } + if(dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD_AST2150){ + goto CBR_START; + } + dlli = dllmin[0] + (((dllmax[0] - dllmin[0]) * 7) >> 4); + MOutdwm(mmiobase, 0x1E6E0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); +} + typedef struct _AST_DRAMStruct { USHORT Index; @@ -867,6 +1049,7 @@ void vInitDRAMReg(ScrnInfoPtr pScrn) ASTRecPtr pAST = ASTPTR(pScrn); ULONG i, ulTemp, ulData; UCHAR jReg; + AST2150DRAMParam param; GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg); @@ -912,7 +1095,7 @@ void vInitDRAMReg(ScrnInfoPtr pScrn) if (pjDRAMRegInfo->Index == 0xFF00) /* Delay function */ { for (i=0; i<15; i++) - usleep(pjDRAMRegInfo->Data); + usleep(pjDRAMRegInfo->Data); } else if ( (pjDRAMRegInfo->Index == 0x0004) && (pAST->jChipType != AST2000) ) { @@ -935,6 +1118,18 @@ void vInitDRAMReg(ScrnInfoPtr pScrn) pjDRAMRegInfo++; } + /* AST2100/2150 DRAM Calibration, ycchen@021511 */ + ulData = *(ULONG *) (pAST->MMIOVirtualAddr + 0x10120); + if (ulData == 0x5061) /* 266MHz */ + { + param.pjMMIOVirtualAddress = pAST->MMIOVirtualAddr; + ulData = *(ULONG *) (pAST->MMIOVirtualAddr + 0x10004); + if (ulData & 0x40) + CBRDLLI_AST2150(¶m, 16); /* 16bits */ + else + CBRDLLI_AST2150(¶m, 32); /* 32bits */ + } + switch (pAST->jChipType) { case AST2000: @@ -990,36 +1185,21 @@ typedef struct _AST2300DRAMParam { ULONG REG_IOZ; ULONG REG_DQIDLY; ULONG REG_FREQ; + ULONG MADJ_MAX; + ULONG DLL2_FINETUNE_STEP; } AST2300DRAMParam, *PAST2300DRAMParam; -__inline ULONG MIndwm(UCHAR *mmiobase, ULONG r) -{ - *(ULONG *) (mmiobase + 0xF004) = r & 0xFFFF0000; - *(ULONG *) (mmiobase + 0xF000) = 0x1; - - return ( *(volatile ULONG *) (mmiobase + 0x10000 + (r & 0x0000FFFF)) ); - -} - -__inline void MOutdwm(UCHAR *mmiobase, ULONG r, ULONG v) -{ - - *(ULONG *) (mmiobase + 0xF004) = r & 0xFFFF0000; - *(ULONG *) (mmiobase + 0xF000) = 0x1; - - *(volatile ULONG *) (mmiobase + 0x10000 + (r & 0x0000FFFF)) = v; -} - /* * DQSI DLL CBR Setting */ -#define CBR_SIZE1 (256 - 1) -#define CBR_SIZE2 ((256 << 10) - 1) +#define CBR_SIZE1 ((4 << 10) - 1) +#define CBR_SIZE2 ((64 << 10) - 1) #define CBR_PASSNUM 5 #define CBR_PASSNUM2 5 +#define CBR_THRESHOLD 10 +#define CBR_THRESHOLD2 10 #define TIMEOUT 5000000 - #define CBR_PATNUM 8 ULONG pattern[8] ={ @@ -1027,10 +1207,10 @@ ULONG pattern[8] ={ 0xCC33CC33, 0xAA55AA55, 0x88778877, -0x4D8223F3, -0x7EE02E83, -0x59E21CFB, -0x6ABB60C0}; +0x92CC4D6E, +0x543D3CDE, +0xF1E843C7, +0x7C61D253}; int MMCTestBurst(PAST2300DRAMParam param, ULONG datagen) { @@ -1056,6 +1236,29 @@ int MMCTestBurst(PAST2300DRAMParam param, ULONG datagen) return(1); } +int MMCTestBurst2(PAST2300DRAMParam param, ULONG datagen) +{ + ULONG data, timeout; + UCHAR *mmiobase; + + mmiobase = param->pjMMIOVirtualAddress; + + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000041 | (datagen << 3)); + timeout = 0; + do{ + data = MIndwm(mmiobase, 0x1E6E0070) & 0x1000; + if(++timeout > TIMEOUT){ + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(-1); + } + }while(!data); + data = MIndwm(mmiobase, 0x1E6E0078); + data = (data | (data >> 16)) & 0xFFFF; + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(data); +} + int MMCTestSingle(PAST2300DRAMParam param, ULONG datagen) { ULONG data, timeout; @@ -1080,38 +1283,67 @@ int MMCTestSingle(PAST2300DRAMParam param, ULONG datagen) return(1); } -int CBRTest(PAST2300DRAMParam param, ULONG pattern) +int MMCTestSingle2(PAST2300DRAMParam param, ULONG datagen) +{ + ULONG data, timeout; + UCHAR *mmiobase; + + mmiobase = param->pjMMIOVirtualAddress; + + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000005 | (datagen << 3)); + timeout = 0; + do{ + data = MIndwm(mmiobase, 0x1E6E0070) & 0x1000; + if(++timeout > TIMEOUT){ + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(-1); + } + }while(!data); + data = MIndwm(mmiobase, 0x1E6E0078); + data = (data | (data >> 16)) & 0xFFFF; + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(data); +} + +int CBRTest(PAST2300DRAMParam param) { - ULONG i,retry; ULONG data; UCHAR *mmiobase; mmiobase = param->pjMMIOVirtualAddress; - MOutdwm(mmiobase, 0x1E6E007C, pattern); - if(!MMCTestBurst(param,0)) return(0); - if(!MMCTestSingle(param,0)) return(0); - if(!MMCTestBurst(param,1)) return(0); - if(!MMCTestBurst(param,2)) return(0); - if(!MMCTestBurst(param,3)) return(0); - if(!MMCTestBurst(param,4)) return(0); - if(!MMCTestBurst(param,5)) return(0); - if(!MMCTestBurst(param,6)) return(0); - if(!MMCTestBurst(param,7)) return(0); + data = MMCTestSingle2(param, 0); if((data & 0xff) && (data & 0xff00)) return(0); + data |= MMCTestBurst2(param, 00); if((data & 0xff) && (data & 0xff00)) return(0); + data |= MMCTestBurst2(param, 01); if((data & 0xff) && (data & 0xff00)) return(0); + data |= MMCTestBurst2(param, 02); if((data & 0xff) && (data & 0xff00)) return(0); + data |= MMCTestBurst2(param, 03); if((data & 0xff) && (data & 0xff00)) return(0); + data |= MMCTestBurst2(param, 04); if((data & 0xff) && (data & 0xff00)) return(0); + data |= MMCTestBurst2(param, 05); if((data & 0xff) && (data & 0xff00)) return(0); + data |= MMCTestBurst2(param, 06); if((data & 0xff) && (data & 0xff00)) return(0); + data |= MMCTestBurst2(param, 07); if((data & 0xff) && (data & 0xff00)) return(0); + if(!data) return(3); + else if(data & 0xff) return(2); + return(1); } -int CBRScan(PAST2300DRAMParam param, ULONG testsize) +int CBRScan(PAST2300DRAMParam param) { - ULONG patcnt, loop; + ULONG data, data2, patcnt, loop; UCHAR *mmiobase; mmiobase = param->pjMMIOVirtualAddress; - MOutdwm(mmiobase, 0x1E6E0074, testsize); + data2 = 3; for(patcnt = 0;patcnt < CBR_PATNUM;patcnt++){ + MOutdwm(mmiobase, 0x1E6E007C, pattern[patcnt]); for(loop = 0;loop < CBR_PASSNUM2;loop++){ - if(CBRTest(param,pattern[patcnt])){ + if((data = CBRTest(param)) != 0){ + data2 &= data; + if(!data2){ + return(0); + } break; } } @@ -1119,33 +1351,37 @@ int CBRScan(PAST2300DRAMParam param, ULONG testsize) return(0); } } - return(1); + return(data2); } -ULONG CBRTest2(PAST2300DRAMParam param, ULONG pattern) +ULONG CBRTest2(PAST2300DRAMParam param) { - ULONG errorbit = 0x0; + ULONG data; UCHAR *mmiobase; mmiobase = param->pjMMIOVirtualAddress; - MOutdwm(mmiobase, 0x1E6E007C, pattern); - if(!MMCTestBurst(param,0)) errorbit |= MIndwm(mmiobase, 0x1E6E0078); - if(!MMCTestSingle(param,0)) errorbit |= MIndwm(mmiobase, 0x1E6E0078); - return(errorbit); + data = MMCTestBurst2(param, 0); if(data == 0xffff) return(0); + data |= MMCTestSingle2(param, 0); if(data == 0xffff) return(0); + return(~data & 0xffff); } -int CBRScan2(PAST2300DRAMParam param, ULONG testsize, ULONG errormask) +ULONG CBRScan2(PAST2300DRAMParam param) { - ULONG patcnt, loop, data; + ULONG data, data2, patcnt, loop; UCHAR *mmiobase; mmiobase = param->pjMMIOVirtualAddress; - MOutdwm(mmiobase, 0x1E6E0074, testsize); + data2 = 0xffff; for(patcnt = 0;patcnt < CBR_PATNUM;patcnt++){ + MOutdwm(mmiobase, 0x1E6E007C, pattern[patcnt]); for(loop = 0;loop < CBR_PASSNUM2;loop++){ - if(!(data = CBRTest2(param, pattern[patcnt]) & errormask)){ + if((data = CBRTest2(param)) != 0){ + data2 &= data; + if(!data2){ + return(0); + } break; } } @@ -1153,175 +1389,410 @@ int CBRScan2(PAST2300DRAMParam param, ULONG testsize, ULONG errormask) return(0); } } - return(1); + return(data2); } void finetuneDQI(PAST2300DRAMParam param) { - ULONG gold_sadj, dqbit, dllmin, dllmax, dlli, errormask, data, cnt; + ULONG gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt; UCHAR *mmiobase; mmiobase = param->pjMMIOVirtualAddress; - gold_sadj = (MIndwm(mmiobase, 0x1E6E0024) >> 16) & 0xff; - - errormask = 0x00010001; - for(dqbit = 0;dqbit < 16;dqbit++){ - dllmin = 0xff; - dllmax = 0x0; - for(dlli = 0;dlli < 76;dlli++){ - MOutdwm(mmiobase, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); - /* Wait DQSI latch phase calibration */ - MOutdwm(mmiobase, 0x1E6E0074, 0x00000020); - MOutdwm(mmiobase, 0x1E6E0070, 0x00000003); - do{ - data = MIndwm(mmiobase, 0x1E6E0070); - }while(!(data & 0x00001000)); - MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + gold_sadj[0] = (MIndwm(mmiobase, 0x1E6E0024) >> 16) & 0xffff; + gold_sadj[1] = gold_sadj[0] >> 8; + gold_sadj[0] = gold_sadj[0] & 0xff; + gold_sadj[0] = (gold_sadj[0] + gold_sadj[1]) >> 1; + gold_sadj[1] = gold_sadj[0]; + + for(cnt = 0;cnt < 16;cnt++){ + dllmin[cnt] = 0xff; + dllmax[cnt] = 0x0; + } + passcnt = 0; + for(dlli = 0;dlli < 76;dlli++){ + MOutdwm(mmiobase, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); + /* Wait DQSI latch phase calibration */ + MOutdwm(mmiobase, 0x1E6E0074, 0x00000010); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000003); + do{ + data = MIndwm(mmiobase, 0x1E6E0070); + }while(!(data & 0x00001000)); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); - for(cnt = 0;cnt < CBR_PASSNUM;cnt++){ - if(CBRScan2(param, CBR_SIZE1,errormask)){ - break; + MOutdwm(mmiobase, 0x1E6E0074, CBR_SIZE1); + data = CBRScan2(param); + if(data != 0){ + mask = 0x00010001; + for(cnt = 0;cnt < 16;cnt++){ + if(data & mask){ + if(dllmin[cnt] > dlli){ + dllmin[cnt] = dlli; + } + if(dllmax[cnt] < dlli){ + dllmax[cnt] = dlli; + } } + mask <<= 1; } - if(cnt < CBR_PASSNUM){ - if(dllmin > dlli){ - dllmin = dlli; + passcnt++; + }else if(passcnt >= CBR_THRESHOLD){ + break; + } + } + data = 0; + for(cnt = 0;cnt < 8;cnt++){ + data >>= 3; + if((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)){ + dlli = (dllmin[cnt] + dllmax[cnt]) >> 1; + if(gold_sadj[0] >= dlli){ + dlli = (gold_sadj[0] - dlli) >> 1; + if(dlli > 3){ + dlli = 3; } - if(dllmax < dlli){ - dllmax = dlli; + }else{ + dlli = (dlli - gold_sadj[0]) >> 1; + if(dlli > 4){ + dlli = 4; } - }else if(dlli > dllmin){ - break; + dlli = (8 - dlli) & 0x7; } + data |= dlli << 21; } - errormask = errormask << 1; - dlli = (dllmin + dllmax) >> 1; - if(gold_sadj >= dlli){ - dlli = (gold_sadj - dlli) >> 1; - if(dlli > 3){ - dlli = 3; + } + MOutdwm(mmiobase, 0x1E6E0080, data); + + data = 0; + for(cnt = 8;cnt < 16;cnt++){ + data >>= 3; + if((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)){ + dlli = (dllmin[cnt] + dllmax[cnt]) >> 1; + if(gold_sadj[1] >= dlli){ + dlli = (gold_sadj[1] - dlli) >> 1; + if(dlli > 3){ + dlli = 3; + }else{ + dlli = (dlli - 1) & 0x7; + } }else{ - dlli &= 0x3; + dlli = (dlli - gold_sadj[1]) >> 1; + dlli += 1; + if(dlli > 4){ + dlli = 4; + } + dlli = (8 - dlli) & 0x7; } - }else{ - dlli = (dlli - gold_sadj) >> 1; - if(dlli > 4){ - dlli = 4; + data |= dlli << 21; + } + } + MOutdwm(mmiobase, 0x1E6E0084, data); + +} /* finetuneDQI */ + +void finetuneDQI_L(PAST2300DRAMParam param) +{ + ULONG gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt; + UCHAR *mmiobase; + + mmiobase = param->pjMMIOVirtualAddress; + + FINETUNE_START: + for(cnt = 0;cnt < 16;cnt++){ + dllmin[cnt] = 0xff; + dllmax[cnt] = 0x0; + } + passcnt = 0; + for(dlli = 0;dlli < 76;dlli++){ + MOutdwm(mmiobase, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); + /* Wait DQSI latch phase calibration */ + MOutdwm(mmiobase, 0x1E6E0074, 0x00000010); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000003); + do{ + data = MIndwm(mmiobase, 0x1E6E0070); + }while(!(data & 0x00001000)); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + + MOutdwm(mmiobase, 0x1E6E0074, CBR_SIZE1); + data = CBRScan2(param); + if(data != 0){ + mask = 0x00010001; + for(cnt = 0;cnt < 16;cnt++){ + if(data & mask){ + if(dllmin[cnt] > dlli){ + dllmin[cnt] = dlli; + } + if(dllmax[cnt] < dlli){ + dllmax[cnt] = dlli; + } + } + mask <<= 1; + } + passcnt++; + }else if(passcnt >= CBR_THRESHOLD2){ + break; + } + } + gold_sadj[0] = 0x0; + passcnt = 0; + for(cnt = 0;cnt < 16;cnt++){ + if((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)){ + gold_sadj[0] += dllmin[cnt]; + passcnt++; + } + } + if(passcnt != 16){ + goto FINETUNE_START; + } + gold_sadj[0] = gold_sadj[0] >> 4; + gold_sadj[1] = gold_sadj[0]; + + data = 0; + for(cnt = 0;cnt < 8;cnt++){ + data >>= 3; + if((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)){ + dlli = dllmin[cnt]; + if(gold_sadj[0] >= dlli){ + dlli = ((gold_sadj[0] - dlli) * 19) >> 5; + if(dlli > 3){ + dlli = 3; + } }else{ - dlli &= 0x7; + dlli = ((dlli - gold_sadj[0]) * 19) >> 5; + if(dlli > 4){ + dlli = 4; + } + dlli = (8 - dlli) & 0x7; } - dlli = (0-dlli) & 0x7; + data |= dlli << 21; } - dlli = dlli << ((dqbit & 0x7) * 3); - if(dqbit < 8){ - MOutdwm(mmiobase, 0x1E6E0080, MIndwm(mmiobase, 0x1E6E0080) | dlli); - }else{ - MOutdwm(mmiobase, 0x1E6E0084, MIndwm(mmiobase, 0x1E6E0084) | dlli); + } + MOutdwm(mmiobase, 0x1E6E0080, data); + + data = 0; + for(cnt = 8;cnt < 16;cnt++){ + data >>= 3; + if((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)){ + dlli = dllmin[cnt]; + if(gold_sadj[1] >= dlli){ + dlli = ((gold_sadj[1] - dlli) * 19) >> 5; + if(dlli > 3){ + dlli = 3; + }else{ + dlli = (dlli - 1) & 0x7; + } + }else{ + dlli = ((dlli - gold_sadj[1]) * 19) >> 5; + dlli += 1; + if(dlli > 4){ + dlli = 4; + } + dlli = (8 - dlli) & 0x7; + } + data |= dlli << 21; } } -} + MOutdwm(mmiobase, 0x1E6E0084, data); -void CBRDLL2(PAST2300DRAMParam param) +} /* finetuneDQI_L */ + +void finetuneDQI_L2(PAST2300DRAMParam param) { - ULONG dllmin, dllmax, dlli, cnt, data, data2; + ULONG gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, data2; UCHAR *mmiobase; mmiobase = param->pjMMIOVirtualAddress; - CBR_START: - dllmin = 0xff; - dllmax = 0x0; + for(cnt = 0;cnt < 16;cnt++){ + dllmin[cnt] = 0xff; + dllmax[cnt] = 0x0; + } + passcnt = 0; for(dlli = 0;dlli < 76;dlli++){ - MOutdwm(mmiobase, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); + MOutdwm(mmiobase, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); /* Wait DQSI latch phase calibration */ - MOutdwm(mmiobase, 0x1E6E0074, 0x00000020); + MOutdwm(mmiobase, 0x1E6E0074, 0x00000010); MOutdwm(mmiobase, 0x1E6E0070, 0x00000003); do{ data = MIndwm(mmiobase, 0x1E6E0070); }while(!(data & 0x00001000)); MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); - for(cnt = 0;cnt < CBR_PASSNUM;cnt++){ - if(CBRScan(param, CBR_SIZE1)){ - break; + MOutdwm(mmiobase, 0x1E6E0074, CBR_SIZE2); + data = CBRScan2(param); + if(data != 0){ + mask = 0x00010001; + for(cnt = 0;cnt < 16;cnt++){ + if(data & mask){ + if(dllmin[cnt] > dlli){ + dllmin[cnt] = dlli; + } + if(dllmax[cnt] < dlli){ + dllmax[cnt] = dlli; + } + } + mask <<= 1; } + passcnt++; + }else if(passcnt >= CBR_THRESHOLD2){ + break; } - if(cnt < CBR_PASSNUM){ - if(dllmin > dlli){ - dllmin = dlli; + } + gold_sadj[0] = 0x0; + gold_sadj[1] = 0xFF; + for(cnt = 0;cnt < 8;cnt++){ + if((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)){ + if(gold_sadj[0] < dllmin[cnt]){ + gold_sadj[0] = dllmin[cnt]; } - if(dllmax < dlli){ - dllmax = dlli; + if(gold_sadj[1] > dllmax[cnt]){ + gold_sadj[1] = dllmax[cnt]; } - }else if(dlli > dllmin){ - break; } } - if(dllmax != 0 && (dllmax-dllmin) < 10){ - goto CBR_START; + gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1; + gold_sadj[1] = MIndwm(mmiobase, 0x1E6E0080); + + data = 0; + for(cnt = 0;cnt < 8;cnt++){ + data >>= 3; + data2 = gold_sadj[1] & 0x7; + gold_sadj[1] >>= 3; + if((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)){ + dlli = (dllmin[cnt] + dllmax[cnt]) >> 1; + if(gold_sadj[0] >= dlli){ + dlli = (gold_sadj[0] - dlli) >> 1; + if(dlli > 0){ + dlli = 1; + } + if(data2 != 3){ + data2 = (data2 + dlli) & 0x7; + } + }else{ + dlli = (dlli - gold_sadj[0]) >> 1; + if(dlli > 0){ + dlli = 1; + } + if(data2 != 4){ + data2 = (data2 - dlli) & 0x7; + } + } + } + data |= data2 << 21; } - /* dlli = dllmin + (int)((float)(dllmax - dllmin) * 0.5); */ - dlli = (dllmin + dllmax) >> 1; - MOutdwm(mmiobase, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); + MOutdwm(mmiobase, 0x1E6E0080, data); + + gold_sadj[0] = 0x0; + gold_sadj[1] = 0xFF; + for(cnt = 8;cnt < 16;cnt++){ + if((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)){ + if(gold_sadj[0] < dllmin[cnt]){ + gold_sadj[0] = dllmin[cnt]; + } + if(gold_sadj[1] > dllmax[cnt]){ + gold_sadj[1] = dllmax[cnt]; + } + } + } + gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1; + gold_sadj[1] = MIndwm(mmiobase, 0x1E6E0084); - finetuneDQI(param); + data = 0; + for(cnt = 8;cnt < 16;cnt++){ + data >>= 3; + data2 = gold_sadj[1] & 0x7; + gold_sadj[1] >>= 3; + if((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)){ + dlli = (dllmin[cnt] + dllmax[cnt]) >> 1; + if(gold_sadj[0] >= dlli){ + dlli = (gold_sadj[0] - dlli) >> 1; + if(dlli > 0){ + dlli = 1; + } + if(data2 != 3){ + data2 = (data2 + dlli) & 0x7; + } + }else{ + dlli = (dlli - gold_sadj[0]) >> 1; + if(dlli > 0){ + dlli = 1; + } + if(data2 != 4){ + data2 = (data2 - dlli) & 0x7; + } + } + } + data |= data2 << 21; + } + MOutdwm(mmiobase, 0x1E6E0084, data); + +} /* finetuneDQI_L2 */ + +void CBRDLL2(PAST2300DRAMParam param) +{ + ULONG dllmin[2], dllmax[2], dlli, data, data2, passcnt; + UCHAR *mmiobase; + + mmiobase = param->pjMMIOVirtualAddress; + + finetuneDQI_L(param); + finetuneDQI_L2(param); CBR_START2: - dllmin = 0xff; - dllmax = 0x0; + dllmin[0] = dllmin[1] = 0xff; + dllmax[0] = dllmax[1] = 0x0; + passcnt = 0; for(dlli = 0;dlli < 76;dlli++){ MOutdwm(mmiobase, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); /* Wait DQSI latch phase calibration */ - MOutdwm(mmiobase, 0x1E6E0074, 0x00000020); + MOutdwm(mmiobase, 0x1E6E0074, 0x00000010); MOutdwm(mmiobase, 0x1E6E0070, 0x00000003); do{ data = MIndwm(mmiobase, 0x1E6E0070); }while(!(data & 0x00001000)); MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); - for(cnt = 0;cnt < CBR_PASSNUM;cnt++){ - if(CBRScan(param, CBR_SIZE2)){ - break; - } - } - if(cnt < CBR_PASSNUM){ - if(dllmin > dlli){ - dllmin = dlli; + MOutdwm(mmiobase, 0x1E6E0074, CBR_SIZE2); + data = CBRScan(param); + if(data != 0){ + if(data & 0x1){ + if(dllmin[0] > dlli){ + dllmin[0] = dlli; + } + if(dllmax[0] < dlli){ + dllmax[0] = dlli; + } } - if(dllmax < dlli){ - dllmax = dlli; + if(data & 0x2){ + if(dllmin[1] > dlli){ + dllmin[1] = dlli; + } + if(dllmax[1] < dlli){ + dllmax[1] = dlli; + } } - }else if(dlli > dllmin){ + passcnt++; + }else if(passcnt >= CBR_THRESHOLD){ break; } } - if(dllmax != 0 && (dllmax-dllmin) < 10){ + if(dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD){ goto CBR_START2; } - dlli = (dllmin + dllmax) >> 1; - MOutdwm(mmiobase, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); + if(dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD){ + goto CBR_START2; + } + dlli = (dllmin[1] + dllmax[1]) >> 1; + dlli <<= 8; + dlli += (dllmin[0] + dllmax[0]) >> 1; + MOutdwm(mmiobase, 0x1E6E0068, (MIndwm(mmiobase, 0x1E6E0068) & 0xFFFF) | (dlli << 16)); - /* Set fine tune for DLL2 */ - data = (MIndwm(mmiobase, 0x1E6E0080) >> 24) & 0x1F; - MOutdwm(mmiobase, 0x1E6E0024, 0xFF01 | (data << 1)); - data = (MIndwm(mmiobase, 0x1E6E0018) & 0xff80ffff) | (data << 16); - MOutdwm(mmiobase, 0x1E6E0018, data); - do{ - data = MIndwm(mmiobase, 0x1E6E0088); - data2 = MIndwm(mmiobase, 0x1E6E0088); - }while(data != data2); - data = (data >> 16) & 0x3FF; - data2 = 12666667 / data; - data2 += 1000000 / param->REG_PERIOD; - data *= 1000000 / param->REG_PERIOD; - data2 = (data + (data2 >> 1)) / data2; - data = MIndwm(mmiobase, 0x1E6E0024) & 0x80ff; - data |= (data2 & 0x7F) << 8; - MOutdwm(mmiobase, 0x1E6E0024, data); + data = (MIndwm(mmiobase, 0x1E6E0080) >> 24) & 0x1F; + data2 = (MIndwm(mmiobase, 0x1E6E0018) & 0xff80ffff) | (data << 16); + MOutdwm(mmiobase, 0x1E6E0018, data2); + MOutdwm(mmiobase, 0x1E6E0024, 0x8001 | (data << 1) | (param->DLL2_FINETUNE_STEP << 8)); /* Wait DQSI latch phase calibration */ - MOutdwm(mmiobase, 0x1E6E0074, 0x00000020); + MOutdwm(mmiobase, 0x1E6E0074, 0x00000010); MOutdwm(mmiobase, 0x1E6E0070, 0x00000003); do{ data = MIndwm(mmiobase, 0x1E6E0070); @@ -1332,128 +1803,199 @@ void CBRDLL2(PAST2300DRAMParam param) data = MIndwm(mmiobase, 0x1E6E0070); }while(!(data & 0x00001000)); MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); -} +} /* CBRDLL2 */ void GetDDR2Info(PAST2300DRAMParam param) { UCHAR *mmiobase; + ULONG trap, TRAP_AC2, TRAP_MRS; mmiobase = param->pjMMIOVirtualAddress; - MOutdwm(mmiobase, 0x1E6E2000, 0x1688A8A8); + + /* Ger trap info */ + trap = (MIndwm(mmiobase, 0x1E6E2070) >> 25) & 0x3; + TRAP_AC2 = (trap << 20) | (trap << 16); + TRAP_AC2 += 0x00110000; + TRAP_MRS = 0x00000040 | (trap << 4); + param->REG_MADJ = 0x00034C4C; - param->REG_SADJ = 0x00001400; - param->REG_DRV = 0x000000F0; - param->REG_PERIOD = param->DRAM_Freq; + param->REG_SADJ = 0x00001800; + param->REG_DRV = 0x000000F0; + param->REG_PERIOD = param->DRAM_Freq; param->RODT = 0; switch(param->DRAM_Freq){ case 264 : MOutdwm(mmiobase, 0x1E6E2020, 0x0130); - param->WODT = 0; - param->REG_AC1 = 0x22202513; - param->REG_AC2 = 0x74117011; - param->REG_DQSIC = 0x000000B0; + param->WODT = 0; + param->REG_AC1 = 0x11101513; + param->REG_AC2 = 0x78117011; + param->REG_DQSIC = 0x00000092; param->REG_MRS = 0x00000842; param->REG_EMRS = 0x00000000; - param->REG_DRV = 0x00000000; - param->REG_IOZ = 0x07000099; - param->REG_DQIDLY = 0x0000005C; - param->REG_FREQ = 0x00004DC0; + param->REG_DRV = 0x000000F0; + param->REG_IOZ = 0x00000034; + param->REG_DQIDLY = 0x0000005A; + param->REG_FREQ = 0x00004AC0; + param->MADJ_MAX = 138; + param->DLL2_FINETUNE_STEP = 3; break; case 336 : MOutdwm(mmiobase, 0x1E6E2020, 0x0190); - param->WODT = 0; - param->REG_AC1 = 0x23202714; - param->REG_AC2 = 0x86229016; - param->REG_DQSIC = 0x000000DF; - param->REG_MRS = 0x00000A52; - param->REG_EMRS = 0x00000000; - param->REG_DRV = 0x00000000; - param->REG_IOZ = 0x07000099; - param->REG_DQIDLY = 0x00000075; + param->WODT = 1; + param->REG_AC1 = 0x22202613; + param->REG_AC2 = 0xAA009016 | TRAP_AC2; + param->REG_DQSIC = 0x000000BA; + param->REG_MRS = 0x00000A02 | TRAP_MRS; + param->REG_EMRS = 0x00000040; + param->REG_DRV = 0x000000FA; + param->REG_IOZ = 0x00000034; + param->REG_DQIDLY = 0x00000074; param->REG_FREQ = 0x00004DC0; + param->MADJ_MAX = 96; + param->DLL2_FINETUNE_STEP = 3; + break; + default: + case 396 : MOutdwm(mmiobase, 0x1E6E2020, 0x03F1); + param->WODT = 1; + param->RODT = 0; + param->REG_AC1 = 0x33302714; + param->REG_AC2 = 0xCC00B01B | TRAP_AC2; + param->REG_DQSIC = 0x000000E2; + param->REG_MRS = 0x00000C02 | TRAP_MRS; + param->REG_EMRS = 0x00000040; + param->REG_DRV = 0x000000FA; + param->REG_IOZ = 0x00000034; + param->REG_DQIDLY = 0x00000089; + param->REG_FREQ = 0x000050C0; + param->MADJ_MAX = 96; + param->DLL2_FINETUNE_STEP = 4; + + switch (param->DRAM_ChipID) + { + case DRAMTYPE_512Mx16: + param->REG_AC2 = 0xCC00B016 | TRAP_AC2; + break; + default: + case DRAMTYPE_1Gx16: + param->REG_AC2 = 0xCC00B01B | TRAP_AC2; + break; + case DRAMTYPE_2Gx16: + param->REG_AC2 = 0xCC00B02B | TRAP_AC2; + break; + case DRAMTYPE_4Gx16: + param->REG_AC2 = 0xCC00B03F | TRAP_AC2; + break; + } + break; - default: + case 408 : MOutdwm(mmiobase, 0x1E6E2020, 0x01F0); - param->WODT = 0; - param->RODT = 0; - param->REG_AC1 = 0x33302715; - param->REG_AC2 = 0xA722A01A; - param->REG_DQSIC = 0x0000010F; - param->REG_MRS = 0x00000A52; + param->WODT = 1; + param->RODT = 0; + param->REG_AC1 = 0x33302714; + param->REG_AC2 = 0xCC00B01B | TRAP_AC2; + param->REG_DQSIC = 0x000000E2; + param->REG_MRS = 0x00000C02 | TRAP_MRS; param->REG_EMRS = 0x00000040; - param->REG_DRV = 0x00000000; - param->REG_IOZ = 0x07000099; - param->REG_DQIDLY = 0x0000008E; + param->REG_DRV = 0x000000FA; + param->REG_IOZ = 0x00000034; + param->REG_DQIDLY = 0x00000089; param->REG_FREQ = 0x000050C0; + param->MADJ_MAX = 96; + param->DLL2_FINETUNE_STEP = 4; + + switch (param->DRAM_ChipID) + { + case DRAMTYPE_512Mx16: + param->REG_AC2 = 0xCC00B016 | TRAP_AC2; + break; + default: + case DRAMTYPE_1Gx16: + param->REG_AC2 = 0xCC00B01B | TRAP_AC2; + break; + case DRAMTYPE_2Gx16: + param->REG_AC2 = 0xCC00B02B | TRAP_AC2; + break; + case DRAMTYPE_4Gx16: + param->REG_AC2 = 0xCC00B03F | TRAP_AC2; + break; + } + break; case 456 : MOutdwm(mmiobase, 0x1E6E2020, 0x0230); - param->WODT = 0; - param->REG_AC1 = 0x33302816; - param->REG_AC2 = 0xB844B01D; - param->REG_DQSIC = 0x0000012F; - param->REG_MRS = 0x00000C72; + param->WODT = 0; + param->REG_AC1 = 0x33302815; + param->REG_AC2 = 0xCD44B01E; + param->REG_DQSIC = 0x000000FC; + param->REG_MRS = 0x00000E72; param->REG_EMRS = 0x00000000; param->REG_DRV = 0x00000000; - param->REG_IOZ = 0x07000000; - param->REG_DQIDLY = 0x0000009F; + param->REG_IOZ = 0x00000034; + param->REG_DQIDLY = 0x00000097; param->REG_FREQ = 0x000052C0; + param->MADJ_MAX = 88; + param->DLL2_FINETUNE_STEP = 3; break; case 504 : MOutdwm(mmiobase, 0x1E6E2020, 0x0261); - param->WODT = 1; - param->RODT = 1; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x34302916; - param->REG_AC2 = 0xC944D01F; - param->REG_DQSIC = 0x0000014F; - param->REG_MRS = 0x00000C72; + param->WODT = 1; + param->RODT = 1; + param->REG_AC1 = 0x33302815; + param->REG_AC2 = 0xDE44C022; + param->REG_DQSIC = 0x00000117; + param->REG_MRS = 0x00000E72; param->REG_EMRS = 0x00000040; - param->REG_DRV = 0x00000000; - param->REG_IOZ = 0x07000000; - param->REG_DQIDLY = 0x000000B0; + param->REG_DRV = 0x0000000A; + param->REG_IOZ = 0x00000045; + param->REG_DQIDLY = 0x000000A0; param->REG_FREQ = 0x000054C0; + param->MADJ_MAX = 79; + param->DLL2_FINETUNE_STEP = 3; break; case 528 : MOutdwm(mmiobase, 0x1E6E2020, 0x0120); - param->WODT = 1; - param->RODT = 1; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x44403916; - param->REG_AC2 = 0xD944D01F; - param->REG_DQSIC = 0x0000015F; - param->REG_MRS = 0x00000C72; - param->REG_EMRS = 0x00000040; - param->REG_DRV = 0x00000000; - param->REG_IOZ = 0x07000011; - param->REG_DQIDLY = 0x000000B9; + param->WODT = 1; + param->RODT = 1; + param->REG_AC1 = 0x33302815; + param->REG_AC2 = 0xEF44D024; + param->REG_DQSIC = 0x00000125; + param->REG_MRS = 0x00000E72; + param->REG_EMRS = 0x00000004; + param->REG_DRV = 0x000000F9; + param->REG_IOZ = 0x00000045; + param->REG_DQIDLY = 0x000000A7; param->REG_FREQ = 0x000055C0; + param->MADJ_MAX = 76; + param->DLL2_FINETUNE_STEP = 3; break; case 552 : MOutdwm(mmiobase, 0x1E6E2020, 0x02A1); - param->WODT = 1; - param->RODT = 1; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x44403916; - param->REG_AC2 = 0xD944E01F; - param->REG_DQSIC = 0x0000016F; - param->REG_MRS = 0x00000C72; + param->WODT = 1; + param->RODT = 1; + param->REG_AC1 = 0x43402915; + param->REG_AC2 = 0xFF44E025; + param->REG_DQSIC = 0x00000132; + param->REG_MRS = 0x00000E72; param->REG_EMRS = 0x00000040; - param->REG_DRV = 0x00000000; - param->REG_IOZ = 0x07000000; - param->REG_DQIDLY = 0x000000C1; - param->REG_FREQ = 0x000057C0; + param->REG_DRV = 0x0000000A; + param->REG_IOZ = 0x00000045; + param->REG_DQIDLY = 0x000000AD; + param->REG_FREQ = 0x000056C0; + param->MADJ_MAX = 76; + param->DLL2_FINETUNE_STEP = 3; break; case 576 : MOutdwm(mmiobase, 0x1E6E2020, 0x0140); - param->WODT = 1; - param->RODT = 1; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x44403916; - param->REG_AC2 = 0xEA44E01F; - param->REG_DQSIC = 0x0000017F; - param->REG_MRS = 0x00000C72; - param->REG_EMRS = 0x00000040; - param->REG_DRV = 0x00000000; - param->REG_IOZ = 0x07000000; - param->REG_DQIDLY = 0x000000CA; + param->WODT = 1; + param->RODT = 1; + param->REG_AC1 = 0x43402915; + param->REG_AC2 = 0xFF44E027; + param->REG_DQSIC = 0x0000013F; + param->REG_MRS = 0x00000E72; + param->REG_EMRS = 0x00000004; + param->REG_DRV = 0x000000F5; + param->REG_IOZ = 0x00000045; + param->REG_DQIDLY = 0x000000B3; param->REG_FREQ = 0x000057C0; + param->MADJ_MAX = 76; + param->DLL2_FINETUNE_STEP = 3; break; } @@ -1496,129 +2038,191 @@ void GetDDR2Info(PAST2300DRAMParam param) void GetDDR3Info(PAST2300DRAMParam param) { UCHAR *mmiobase; + ULONG trap, TRAP_AC2, TRAP_MRS; mmiobase = param->pjMMIOVirtualAddress; + MOutdwm(mmiobase, 0x1E6E2000, 0x1688A8A8); + + /* Ger trap info */ + trap = (MIndwm(mmiobase, 0x1E6E2070) >> 25) & 0x3; + TRAP_AC2 = 0x00020000 + (trap << 16); + TRAP_AC2 |= 0x00300000 +((trap & 0x2) << 19); + TRAP_MRS = 0x00000010 + (trap << 4); + TRAP_MRS |= ((trap & 0x2) << 18); param->REG_MADJ = 0x00034C4C; - param->REG_SADJ = 0x00001600; - param->REG_DRV = 0x000000F0; - param->REG_PERIOD = param->DRAM_Freq; + param->REG_SADJ = 0x00001800; + param->REG_DRV = 0x000000F0; + param->REG_PERIOD = param->DRAM_Freq; param->RODT = 0; - MOutdwm(mmiobase, 0x1E6E2000, 0x1688A8A8); - switch(param->DRAM_Freq){ case 336 : MOutdwm(mmiobase, 0x1E6E2020, 0x0190); - param->WODT = 0; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x23202826; - param->REG_AC2 = 0x85327513; - param->REG_DQSIC = 0x000000DF; - param->REG_MRS = 0x00001410; + param->WODT = 0; + param->REG_AC1 = 0x22202725; + param->REG_AC2 = 0xAA007613 | TRAP_AC2; + param->REG_DQSIC = 0x000000BA; + param->REG_MRS = 0x04001400 | TRAP_MRS; param->REG_EMRS = 0x00000000; - param->REG_IOZ = 0x070000CC; - param->REG_DQIDLY = 0x00000075; + param->REG_IOZ = 0x00000034; + param->REG_DQIDLY = 0x00000074; param->REG_FREQ = 0x00004DC0; + param->MADJ_MAX = 96; + param->DLL2_FINETUNE_STEP = 3; + break; + default: + case 396 : MOutdwm(mmiobase, 0x1E6E2020, 0x03F1); + param->WODT = 1; + param->REG_AC1 = 0x33302825; + param->REG_AC2 = 0xCC009617 | TRAP_AC2; + param->REG_DQSIC = 0x000000E2; + param->REG_MRS = 0x04001600 | TRAP_MRS; + param->REG_EMRS = 0x00000000; + param->REG_IOZ = 0x00000034; + param->REG_DRV = 0x000000FA; + param->REG_DQIDLY = 0x00000089; + param->REG_FREQ = 0x000050C0; + param->MADJ_MAX = 96; + param->DLL2_FINETUNE_STEP = 4; + + switch (param->DRAM_ChipID) + { + default: + case DRAMTYPE_512Mx16: + case DRAMTYPE_1Gx16: + param->REG_AC2 = 0xCC009617 | TRAP_AC2; + break; + case DRAMTYPE_2Gx16: + param->REG_AC2 = 0xCC009622 | TRAP_AC2; + break; + case DRAMTYPE_4Gx16: + param->REG_AC2 = 0xCC00963F | TRAP_AC2; + break; + } + break; - default: + case 408 : MOutdwm(mmiobase, 0x1E6E2020, 0x01F0); - param->WODT = 0; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x33302826; - param->REG_AC2 = 0xA6329516; - param->REG_DQSIC = 0x0000010F; - param->REG_MRS = 0x00001610; + param->WODT = 1; + param->REG_AC1 = 0x33302825; + param->REG_AC2 = 0xCC009617 | TRAP_AC2; + param->REG_DQSIC = 0x000000E2; + param->REG_MRS = 0x04001600 | TRAP_MRS; param->REG_EMRS = 0x00000000; - param->REG_IOZ = 0x070000CC; - param->REG_DQIDLY = 0x0000008E; + param->REG_IOZ = 0x00000034; + param->REG_DRV = 0x000000FA; + param->REG_DQIDLY = 0x00000089; param->REG_FREQ = 0x000050C0; + param->MADJ_MAX = 96; + param->DLL2_FINETUNE_STEP = 4; + + switch (param->DRAM_ChipID) + { + default: + case DRAMTYPE_512Mx16: + case DRAMTYPE_1Gx16: + param->REG_AC2 = 0xCC009617 | TRAP_AC2; + break; + case DRAMTYPE_2Gx16: + param->REG_AC2 = 0xCC009622 | TRAP_AC2; + break; + case DRAMTYPE_4Gx16: + param->REG_AC2 = 0xCC00963F | TRAP_AC2; + break; + } + break; case 456 : MOutdwm(mmiobase, 0x1E6E2020, 0x0230); - param->WODT = 0; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x33302937; - param->REG_AC2 = 0xB7449519; - param->REG_DQSIC = 0x0000012F; - param->REG_MRS = 0x00081630; + param->WODT = 0; + param->REG_AC1 = 0x33302926; + param->REG_AC2 = 0xCD44961A; + param->REG_DQSIC = 0x000000FC; + param->REG_MRS = 0x00081830; param->REG_EMRS = 0x00000000; - param->REG_IOZ = 0x070000CC; - param->REG_DQIDLY = 0x0000009F; + param->REG_IOZ = 0x00000045; + param->REG_DQIDLY = 0x00000097; param->REG_FREQ = 0x000052C0; + param->MADJ_MAX = 88; + param->DLL2_FINETUNE_STEP = 4; break; case 504 : MOutdwm(mmiobase, 0x1E6E2020, 0x0270); - param->WODT = 1; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x33302A37; - param->REG_AC2 = 0xC744A51C; - param->REG_DQSIC = 0x0000014F; - param->REG_MRS = 0x00081830; + param->WODT = 1; + param->REG_AC1 = 0x33302926; + param->REG_AC2 = 0xDE44A61D; + param->REG_DQSIC = 0x00000117; + param->REG_MRS = 0x00081A30; + param->REG_EMRS = 0x00000000; param->REG_IOZ = 0x070000BB; - param->REG_DQIDLY = 0x000000B0; + param->REG_DQIDLY = 0x000000A0; param->REG_FREQ = 0x000054C0; + param->MADJ_MAX = 79; + param->DLL2_FINETUNE_STEP = 4; break; case 528 : MOutdwm(mmiobase, 0x1E6E2020, 0x0290); - param->WODT = 1; - param->RODT = 1; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x33303A37; - param->REG_AC2 = 0xD844B61D; - param->REG_DQSIC = 0x0000015F; + param->WODT = 1; + param->RODT = 1; + param->REG_AC1 = 0x33302926; + param->REG_AC2 = 0xEF44B61E; + param->REG_DQSIC = 0x00000125; param->REG_MRS = 0x00081A30; param->REG_EMRS = 0x00000040; - param->REG_IOZ = 0x070000BB; - param->REG_DQIDLY = 0x000000B9; + param->REG_DRV = 0x000000F5; + param->REG_IOZ = 0x00000023; + param->REG_DQIDLY = 0x00000088; param->REG_FREQ = 0x000055C0; + param->MADJ_MAX = 76; + param->DLL2_FINETUNE_STEP = 3; break; case 576 : MOutdwm(mmiobase, 0x1E6E2020, 0x0140); - param->WODT = 1; - param->RODT = 1; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x43403A27; - param->REG_AC2 = 0xC955C51F; - param->REG_DQSIC = 0x0000017F; - param->REG_MRS = 0x00101A40; + param->REG_MADJ = 0x00136868; + param->REG_SADJ = 0x00004534; + param->WODT = 1; + param->RODT = 1; + param->REG_AC1 = 0x33302A37; + param->REG_AC2 = 0xEF56B61E; + param->REG_DQSIC = 0x0000013F; + param->REG_MRS = 0x00101A50; param->REG_EMRS = 0x00000040; - param->REG_IOZ = 0x070000BB; - param->REG_DQIDLY = 0x000000CA; + param->REG_DRV = 0x000000FA; + param->REG_IOZ = 0x00000023; + param->REG_DQIDLY = 0x00000078; param->REG_FREQ = 0x000057C0; + param->MADJ_MAX = 136; + param->DLL2_FINETUNE_STEP = 3; break; case 600 : MOutdwm(mmiobase, 0x1E6E2020, 0x02E1); - param->WODT = 1; - param->RODT = 1; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x43403B27; - param->REG_AC2 = 0xE955C51F; - param->REG_DQSIC = 0x0000018F; - param->REG_MRS = 0x00101C40; + param->REG_MADJ = 0x00136868; + param->REG_SADJ = 0x00004534; + param->WODT = 1; + param->RODT = 1; + param->REG_AC1 = 0x32302A37; + param->REG_AC2 = 0xDF56B61F; + param->REG_DQSIC = 0x0000014D; + param->REG_MRS = 0x00101A50; param->REG_EMRS = 0x00000004; - param->REG_IOZ = 0x070000BB; - param->REG_DQIDLY = 0x000000D2; + param->REG_DRV = 0x000000F5; + param->REG_IOZ = 0x00000023; + param->REG_DQIDLY = 0x00000078; param->REG_FREQ = 0x000058C0; + param->MADJ_MAX = 132; + param->DLL2_FINETUNE_STEP = 3; break; case 624 : MOutdwm(mmiobase, 0x1E6E2020, 0x0160); - param->WODT = 1; - param->RODT = 1; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x43403B27; - param->REG_AC2 = 0xF955C51F; - param->REG_DQSIC = 0x0000019F; - param->REG_MRS = 0x04101C40; - param->REG_EMRS = 0x00000040; - param->REG_IOZ = 0x070000BB; - param->REG_DQIDLY = 0x000000DA; + param->REG_MADJ = 0x00136868; + param->REG_SADJ = 0x00004534; + param->WODT = 1; + param->RODT = 1; + param->REG_AC1 = 0x32302A37; + param->REG_AC2 = 0xEF56B621; + param->REG_DQSIC = 0x0000015A; + param->REG_MRS = 0x02101A50; + param->REG_EMRS = 0x00000004; + param->REG_DRV = 0x000000F5; + param->REG_IOZ = 0x00000034; + param->REG_DQIDLY = 0x00000078; param->REG_FREQ = 0x000059C0; - break; - case 648 : MOutdwm(mmiobase, 0x1E6E2020, 0x0321); - param->WODT = 1; - param->REG_SADJ = 0x00001400; - param->REG_AC1 = 0x43403B27; - param->REG_AC2 = 0xFA55D51F; - param->REG_DQSIC = 0x000001AF; - param->REG_MRS = 0x00101C40; - param->REG_IOZ = 0x070000AA; - param->REG_FREQ = 0x00005AC0; - param->REG_DQIDLY = 0x000000E3; - param->REG_SADJ = 0x00001600; + param->MADJ_MAX = 128; + param->DLL2_FINETUNE_STEP = 3; break; } /* switch freq */ @@ -1660,7 +2264,7 @@ void GetDDR3Info(PAST2300DRAMParam param) void DDR2_Init(PAST2300DRAMParam param) { - ULONG data; + ULONG data, data2; UCHAR *mmiobase; mmiobase = param->pjMMIOVirtualAddress; @@ -1670,8 +2274,9 @@ void DDR2_Init(PAST2300DRAMParam param) MOutdwm(mmiobase, 0x1E6E0024, 0x00000000); MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ); MOutdwm(mmiobase, 0x1E6E0068, param->REG_SADJ); - usleep(10); /* Delay 2 us */ - MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ | 0x40000); + usleep(10); + MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ | 0xC0000); + usleep(10); MOutdwm(mmiobase, 0x1E6E0004, param->DRAM_CONFIG); MOutdwm(mmiobase, 0x1E6E0008, 0x90040f); @@ -1680,59 +2285,75 @@ void DDR2_Init(PAST2300DRAMParam param) MOutdwm(mmiobase, 0x1E6E0020, param->REG_DQSIC); MOutdwm(mmiobase, 0x1E6E0080, 0x00000000); MOutdwm(mmiobase, 0x1E6E0084, 0x00000000); - MOutdwm(mmiobase, 0x1E6E0088, param->REG_DQIDLY); /* fine tune required */ - MOutdwm(mmiobase, 0x1E6E0018, 0x4040C130); - MOutdwm(mmiobase, 0x1E6E0018, 0x20404330); /* fine tune required */ + MOutdwm(mmiobase, 0x1E6E0088, param->REG_DQIDLY); + MOutdwm(mmiobase, 0x1E6E0018, 0x4040A130); + MOutdwm(mmiobase, 0x1E6E0018, 0x20402330); MOutdwm(mmiobase, 0x1E6E0038, 0x00000000); - MOutdwm(mmiobase, 0x1E6E0040, 0xFF808000); /* fine tune required */ - MOutdwm(mmiobase, 0x1E6E0044, 0x88848466); /* fine tune required */ - MOutdwm(mmiobase, 0x1E6E0048, 0x44440008); /* fine tune required */ + MOutdwm(mmiobase, 0x1E6E0040, 0xFF808000); + MOutdwm(mmiobase, 0x1E6E0044, 0x88848466); + MOutdwm(mmiobase, 0x1E6E0048, 0x44440008); MOutdwm(mmiobase, 0x1E6E004C, 0x00000000); MOutdwm(mmiobase, 0x1E6E0050, 0x80000000); MOutdwm(mmiobase, 0x1E6E0050, 0x00000000); MOutdwm(mmiobase, 0x1E6E0054, 0); - if(param->RODT) - { - if (param->ODT == 75) - MOutdwm(mmiobase, 0x1E6E0060, param->REG_DRV | 0x5); - else - MOutdwm(mmiobase, 0x1E6E0060, param->REG_DRV | 0xA); - }else - { - MOutdwm(mmiobase, 0x1E6E0060, param->REG_DRV); - } + MOutdwm(mmiobase, 0x1E6E0060, param->REG_DRV); + MOutdwm(mmiobase, 0x1E6E006C, param->REG_IOZ); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0074, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0078, 0x00000000); + MOutdwm(mmiobase, 0x1E6E007C, 0x00000000); + /* Wait MCLK2X lock to MCLK */ do{ data = MIndwm(mmiobase, 0x1E6E001C); }while(!(data & 0x08000000)); + MOutdwm(mmiobase, 0x1E6E0034, 0x00000001); + MOutdwm(mmiobase, 0x1E6E000C, 0x00005C04); + usleep(10); + MOutdwm(mmiobase, 0x1E6E000C, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0034, 0x00000000); + data = MIndwm(mmiobase, 0x1E6E001C); data = (data >> 8) & 0xff; - if(data > 61 || data < 15){ - data = MIndwm(mmiobase, 0x1E6E0018) ^ 0x300; + while((data & 0x08) || ((data & 0x7) < 2) || (data < 4)){ + data2 = (MIndwm(mmiobase, 0x1E6E0064) & 0xfff3ffff) + 4; + if((data2 & 0xff) > param->MADJ_MAX){ + break; + } + MOutdwm(mmiobase, 0x1E6E0064, data2); + if(data2 & 0x00100000){ + data2 = ((data2 & 0xff) >> 3) + 3; + }else{ + data2 = ((data2 & 0xff) >> 2) + 5; + } + data = MIndwm(mmiobase, 0x1E6E0068) & 0xffff00ff; + data2 += data & 0xff; + data = data | (data2 << 8); + MOutdwm(mmiobase, 0x1E6E0068, data); + usleep(10); + MOutdwm(mmiobase, 0x1E6E0064, MIndwm(mmiobase, 0x1E6E0064) | 0xC0000); + usleep(10); + data = MIndwm(mmiobase, 0x1E6E0018) & 0xfffff1ff; MOutdwm(mmiobase, 0x1E6E0018, data); - MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ); - usleep(10); /* Delay 2 us */ data = data | 0x200; MOutdwm(mmiobase, 0x1E6E0018, data); - MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ | 0x40000); do{ data = MIndwm(mmiobase, 0x1E6E001C); }while(!(data & 0x08000000)); + + MOutdwm(mmiobase, 0x1E6E0034, 0x00000001); + MOutdwm(mmiobase, 0x1E6E000C, 0x00005C04); + usleep(10); + MOutdwm(mmiobase, 0x1E6E000C, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0034, 0x00000000); + data = MIndwm(mmiobase, 0x1E6E001C); + data = (data >> 8) & 0xff; } data = MIndwm(mmiobase, 0x1E6E0018) | 0xC00; MOutdwm(mmiobase, 0x1E6E0018, data); - MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ | 0xC0000); - MOutdwm(mmiobase, 0x1E6E006C, param->REG_IOZ); /* fine tune required */ - MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); - MOutdwm(mmiobase, 0x1E6E0074, 0x00000000); - MOutdwm(mmiobase, 0x1E6E0078, 0x00000000); - MOutdwm(mmiobase, 0x1E6E007C, 0x00000000); - /* Wait DQI delay lock */ - do{ - data = MIndwm(mmiobase, 0x1E6E0080); - }while(!(data & 0x40000000)); + MOutdwm(mmiobase, 0x1E6E0034, 0x00000001); MOutdwm(mmiobase, 0x1E6E000C, 0x00000000); - usleep(50); /* Delay 400 us */ + usleep(50); /* Mode Register Setting */ MOutdwm(mmiobase, 0x1E6E002C, param->REG_MRS | 0x100); MOutdwm(mmiobase, 0x1E6E0030, param->REG_EMRS); @@ -1740,7 +2361,7 @@ void DDR2_Init(PAST2300DRAMParam param) MOutdwm(mmiobase, 0x1E6E0028, 0x00000007); MOutdwm(mmiobase, 0x1E6E0028, 0x00000003); MOutdwm(mmiobase, 0x1E6E0028, 0x00000001); - MOutdwm(mmiobase, 0x1E6E000C, 0x00005A08); + MOutdwm(mmiobase, 0x1E6E000C, 0x00005C08); MOutdwm(mmiobase, 0x1E6E002C, param->REG_MRS); MOutdwm(mmiobase, 0x1E6E0028, 0x00000001); MOutdwm(mmiobase, 0x1E6E0030, param->REG_EMRS | 0x380); @@ -1748,10 +2369,10 @@ void DDR2_Init(PAST2300DRAMParam param) MOutdwm(mmiobase, 0x1E6E0030, param->REG_EMRS); MOutdwm(mmiobase, 0x1E6E0028, 0x00000003); - MOutdwm(mmiobase, 0x1E6E000C, 0x7FFF5A01); + MOutdwm(mmiobase, 0x1E6E000C, 0x7FFF5C01); data = 0; if(param->WODT){ - data = 0x700; + data = 0x500; } if(param->RODT){ data = data | 0x3000 | ((param->REG_AC2 & 0x60000) >> 3); @@ -1759,6 +2380,10 @@ void DDR2_Init(PAST2300DRAMParam param) MOutdwm(mmiobase, 0x1E6E0034, data | 0x3); MOutdwm(mmiobase, 0x1E6E0120, param->REG_FREQ); + /* Wait DQI delay lock */ + do{ + data = MIndwm(mmiobase, 0x1E6E0080); + }while(!(data & 0x40000000)); /* Wait DQSI delay lock */ do{ data = MIndwm(mmiobase, 0x1E6E0020); @@ -1766,11 +2391,22 @@ void DDR2_Init(PAST2300DRAMParam param) /* Calibrate the DQSI delay */ CBRDLL2(param); + /* ECC Memory Initialization */ +#ifdef ECC + MOutdwm(mmiobase, 0x1E6E007C, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0070, 0x221); + do{ + data = MIndwm(mmiobase, 0x1E6E0070); + }while(!(data & 0x00001000)); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0050, 0x80000000); + MOutdwm(mmiobase, 0x1E6E0050, 0x00000000); +#endif } void DDR3_Init(PAST2300DRAMParam param) { - ULONG data; + ULONG data, data2; UCHAR *mmiobase; mmiobase = param->pjMMIOVirtualAddress; @@ -1778,10 +2414,13 @@ void DDR3_Init(PAST2300DRAMParam param) MOutdwm(mmiobase, 0x1E6E0000, 0xFC600309); MOutdwm(mmiobase, 0x1E6E0018, 0x00000100); MOutdwm(mmiobase, 0x1E6E0024, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0034, 0x00000000); + usleep(10); MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ); MOutdwm(mmiobase, 0x1E6E0068, param->REG_SADJ); - usleep(10); /* Delay 2 us */ - MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ | 0x40000); + usleep(10); + MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ | 0xC0000); + usleep(10); MOutdwm(mmiobase, 0x1E6E0004, param->DRAM_CONFIG); MOutdwm(mmiobase, 0x1E6E0008, 0x90040f); @@ -1790,60 +2429,75 @@ void DDR3_Init(PAST2300DRAMParam param) MOutdwm(mmiobase, 0x1E6E0020, param->REG_DQSIC); MOutdwm(mmiobase, 0x1E6E0080, 0x00000000); MOutdwm(mmiobase, 0x1E6E0084, 0x00000000); - MOutdwm(mmiobase, 0x1E6E0088, param->REG_DQIDLY); /* fine tune required */ - MOutdwm(mmiobase, 0x1E6E0018, 0x4040C170); - MOutdwm(mmiobase, 0x1E6E0018, 0x20404370); /* fine tune required */ + MOutdwm(mmiobase, 0x1E6E0088, param->REG_DQIDLY); + MOutdwm(mmiobase, 0x1E6E0018, 0x4040A170); + MOutdwm(mmiobase, 0x1E6E0018, 0x20402370); MOutdwm(mmiobase, 0x1E6E0038, 0x00000000); - MOutdwm(mmiobase, 0x1E6E0040, 0xFF808000); /* fine tune required */ - MOutdwm(mmiobase, 0x1E6E0044, 0x88848466); /* fine tune required */ - MOutdwm(mmiobase, 0x1E6E0048, 0x44440008); /* fine tune required */ - MOutdwm(mmiobase, 0x1E6E004C, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0040, 0xFF444444); + MOutdwm(mmiobase, 0x1E6E0044, 0x22222222); + MOutdwm(mmiobase, 0x1E6E0048, 0x22222222); + MOutdwm(mmiobase, 0x1E6E004C, 0x00000002); MOutdwm(mmiobase, 0x1E6E0050, 0x80000000); MOutdwm(mmiobase, 0x1E6E0050, 0x00000000); MOutdwm(mmiobase, 0x1E6E0054, 0); - if(param->RODT) - { - if (param->ODT == 75) - MOutdwm(mmiobase, 0x1E6E0060, param->REG_DRV | 0x5); - else - MOutdwm(mmiobase, 0x1E6E0060, param->REG_DRV | 0xA); - } - else - { - MOutdwm(mmiobase, 0x1E6E0060, param->REG_DRV); - } + MOutdwm(mmiobase, 0x1E6E0060, param->REG_DRV); + MOutdwm(mmiobase, 0x1E6E006C, param->REG_IOZ); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0074, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0078, 0x00000000); + MOutdwm(mmiobase, 0x1E6E007C, 0x00000000); + /* Wait MCLK2X lock to MCLK */ do{ data = MIndwm(mmiobase, 0x1E6E001C); }while(!(data & 0x08000000)); + MOutdwm(mmiobase, 0x1E6E0034, 0x00000001); + MOutdwm(mmiobase, 0x1E6E000C, 0x00005C04); + usleep(10); + MOutdwm(mmiobase, 0x1E6E000C, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0034, 0x00000000); + data = MIndwm(mmiobase, 0x1E6E001C); data = (data >> 8) & 0xff; - if(data > 61 || data < 15){ - data = MIndwm(mmiobase, 0x1E6E0018) ^ 0x300; + while((data & 0x08) || ((data & 0x7) < 2) || (data < 4)){ + data2 = (MIndwm(mmiobase, 0x1E6E0064) & 0xfff3ffff) + 4; + if((data2 & 0xff) > param->MADJ_MAX){ + break; + } + MOutdwm(mmiobase, 0x1E6E0064, data2); + if(data2 & 0x00100000){ + data2 = ((data2 & 0xff) >> 3) + 3; + }else{ + data2 = ((data2 & 0xff) >> 2) + 5; + } + data = MIndwm(mmiobase, 0x1E6E0068) & 0xffff00ff; + data2 += data & 0xff; + data = data | (data2 << 8); + MOutdwm(mmiobase, 0x1E6E0068, data); + usleep(10); + MOutdwm(mmiobase, 0x1E6E0064, MIndwm(mmiobase, 0x1E6E0064) | 0xC0000); + usleep(10); + data = MIndwm(mmiobase, 0x1E6E0018) & 0xfffff1ff; MOutdwm(mmiobase, 0x1E6E0018, data); - MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ); - usleep(10); /* Delay 2 us */ data = data | 0x200; MOutdwm(mmiobase, 0x1E6E0018, data); - MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ | 0x40000); do{ data = MIndwm(mmiobase, 0x1E6E001C); }while(!(data & 0x08000000)); + + MOutdwm(mmiobase, 0x1E6E0034, 0x00000001); + MOutdwm(mmiobase, 0x1E6E000C, 0x00005C04); + usleep(10); + MOutdwm(mmiobase, 0x1E6E000C, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0034, 0x00000000); + data = MIndwm(mmiobase, 0x1E6E001C); + data = (data >> 8) & 0xff; } data = MIndwm(mmiobase, 0x1E6E0018) | 0xC00; MOutdwm(mmiobase, 0x1E6E0018, data); - MOutdwm(mmiobase, 0x1E6E0064, param->REG_MADJ | 0xC0000); - MOutdwm(mmiobase, 0x1E6E006C, param->REG_IOZ); /* fine tune required */ - MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); - MOutdwm(mmiobase, 0x1E6E0074, 0x00000000); - MOutdwm(mmiobase, 0x1E6E0078, 0x00000000); - MOutdwm(mmiobase, 0x1E6E007C, 0x00000000); - /* Wait DQI delay lock */ - do{ - data = MIndwm(mmiobase, 0x1E6E0080); - }while(!(data & 0x40000000)); + MOutdwm(mmiobase, 0x1E6E0034, 0x00000001); MOutdwm(mmiobase, 0x1E6E000C, 0x00000040); - usleep(50); /* Delay 400 us */ + usleep(50); /* Mode Register Setting */ MOutdwm(mmiobase, 0x1E6E002C, param->REG_MRS | 0x100); MOutdwm(mmiobase, 0x1E6E0030, param->REG_EMRS); @@ -1852,19 +2506,23 @@ void DDR3_Init(PAST2300DRAMParam param) MOutdwm(mmiobase, 0x1E6E0028, 0x00000003); MOutdwm(mmiobase, 0x1E6E0028, 0x00000001); MOutdwm(mmiobase, 0x1E6E002C, param->REG_MRS); - MOutdwm(mmiobase, 0x1E6E000C, 0x00005A48); + MOutdwm(mmiobase, 0x1E6E000C, 0x00005C08); MOutdwm(mmiobase, 0x1E6E0028, 0x00000001); - MOutdwm(mmiobase, 0x1E6E000C, 0x7FFF5A81); + MOutdwm(mmiobase, 0x1E6E000C, 0x7FFF5C01); data = 0; if(param->WODT){ - data = 0x700; + data = 0x300; } if(param->RODT){ data = data | 0x3000 | ((param->REG_AC2 & 0x60000) >> 3); } MOutdwm(mmiobase, 0x1E6E0034, data | 0x3); + /* Wait DQI delay lock */ + do{ + data = MIndwm(mmiobase, 0x1E6E0080); + }while(!(data & 0x40000000)); /* Wait DQSI delay lock */ do{ data = MIndwm(mmiobase, 0x1E6E0020); @@ -1873,7 +2531,17 @@ void DDR3_Init(PAST2300DRAMParam param) CBRDLL2(param); MOutdwm(mmiobase, 0x1E6E0120, param->REG_FREQ); - + /* ECC Memory Initialization */ +#ifdef ECC + MOutdwm(mmiobase, 0x1E6E007C, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0070, 0x221); + do{ + data = MIndwm(mmiobase, 0x1E6E0070); + }while(!(data & 0x00001000)); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0050, 0x80000000); + MOutdwm(mmiobase, 0x1E6E0050, 0x00000000); +#endif } void vInitAST2300DRAMReg(ScrnInfoPtr pScrn) @@ -1899,6 +2567,11 @@ void vInitAST2300DRAMReg(ScrnInfoPtr pScrn) do { ; } while (*(volatile ULONG *) (pAST->MMIOVirtualAddr + 0x10000) != 0x01); + + /* Slow down CPU/AHB CLK in VGA only mode */ + ulTemp = *(ULONG *) (pAST->MMIOVirtualAddr + 0x12008); + ulTemp |= 0x73; + *(ULONG *) (pAST->MMIOVirtualAddr + 0x12008) = ulTemp; param.pjMMIOVirtualAddress = pAST->MMIOVirtualAddr; param.DRAM_Type = DDR3; /* DDR3 */ @@ -2211,11 +2884,19 @@ GetVGAEDID(ScrnInfoPtr pScrn, unsigned char *pEDIDBuffer) pjDstEDID = (UCHAR *) pEDIDBuffer; /* Force to DDC2 */ - I2CWriteClock(pAST, 0x01); /* Set Clk Low */ + I2CWriteClock(pAST, 0x01); /* Set Clk High */ I2CDelay(pAST); - I2CDelay(pAST); I2CWriteClock(pAST, 0x00); /* Set Clk Low */ I2CDelay(pAST); + I2CWriteClock(pAST, 0x01); /* Set Clk High */ + I2CDelay(pAST); + + /* Validate SCL */ + if (I2CReadClock(pAST) == 0) /* chk SCL failed */ + { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[GetVGAEDID] Check SCL Failed \n"); + return (FALSE); + } I2CStart(pAST); -- cgit v1.2.3