diff options
| author | Dave Airlie <airlied@nx6125b.(none)> | 2007-05-30 08:02:26 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@nx6125b.(none)> | 2007-05-30 08:02:26 +1000 |
| commit | bff809dc8ed07ac39e9b576a87916486a5e37156 (patch) | |
| tree | 8a9ece8efa49d57ff288953ed84b6b3af890ed4e | |
| parent | 104105fee5c3945d3f210e6a4cb73ab492c61543 (diff) | |
rs480: more unknown regs
Hardcode the values from a working fglrx run, this works for me now
I've no idea what it might do for anyone else
| -rw-r--r-- | src/radeon.h | 3 | ||||
| -rw-r--r-- | src/radeon_driver.c | 15 | ||||
| -rw-r--r-- | src/radeon_reg.h | 4 |
3 files changed, 19 insertions, 3 deletions
diff --git a/src/radeon.h b/src/radeon.h index 3e79c1b2..88402df5 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -318,7 +318,10 @@ typedef struct { CARD32 tv_dac_cntl; + CARD32 rs480_unk_e30; + CARD32 rs480_unk_e34; CARD32 rs480_unk_e38; + CARD32 rs480_unk_e3c; } RADEONSaveRec, *RADEONSavePtr; typedef struct { diff --git a/src/radeon_driver.c b/src/radeon_driver.c index a3d8a033..5eca577a 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -4665,7 +4665,10 @@ static void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); if (info->ChipFamily == CHIP_FAMILY_RS400) { + OUTREG(RADEON_RS480_UNK_e30, restore->rs480_unk_e30); + OUTREG(RADEON_RS480_UNK_e34, restore->rs480_unk_e34); OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38); + OUTREG(RADEON_RS480_UNK_e3c, restore->rs480_unk_e3c); } OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); @@ -5363,8 +5366,12 @@ static void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); - if (info->ChipFamily == CHIP_FAMILY_RS400) + if (info->ChipFamily == CHIP_FAMILY_RS400) { + save->rs480_unk_e30 = INREG(RADEON_RS480_UNK_e30); + save->rs480_unk_e34 = INREG(RADEON_RS480_UNK_e34); save->rs480_unk_e38 = INREG(RADEON_RS480_UNK_e38); + save->rs480_unk_e3c = INREG(RADEON_RS480_UNK_e3c); + } save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); } @@ -6241,8 +6248,10 @@ static Bool RADEONInitCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, #endif if (info->ChipFamily == CHIP_FAMILY_RS400) { - save->rs480_unk_e38 = info->SavedReg.rs480_unk_e38 & ~(0x300); - save->rs480_unk_e38 |= 0x100; + save->rs480_unk_e30 = 0x105DC1CC; /* because I'm worth it */ + save->rs480_unk_e34 = 0x2749D000; /* AMD really should */ + save->rs480_unk_e38 = 0x29ca71dc; /* release docs */ + save->rs480_unk_e3c = 0x28FBC3AC; /* this is so a trade secret */ } return TRUE; diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 476c56b6..01bcec80 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -3127,5 +3127,9 @@ # define RADEON_TVPLL_SLEEP (1 << 3) # define RADEON_TVPLL_REFCLK_SEL (1 << 4) +#define RADEON_RS480_UNK_e30 0xe30 +#define RADEON_RS480_UNK_e34 0xe34 #define RADEON_RS480_UNK_e38 0xe38 +#define RADEON_RS480_UNK_e3c 0xe3c + #endif |