diff options
| author | Michel Daenzer <michel@daenzer.net> | 2006-03-09 15:41:16 +0000 |
|---|---|---|
| committer | Michel Daenzer <michel@daenzer.net> | 2006-03-09 15:41:16 +0000 |
| commit | c637939d3c4ce5cdddbc5200d5ffbca4c3927050 (patch) | |
| tree | 6193fe4be5a13ee361f493a3bc4da0cdb2b6efc6 | |
| parent | 890b95a3ddad7634f3aea635cb236b221e902acc (diff) | |
RN50: Skip modes that exceed memory bandwidth.
Bugzilla #5766 <https://bugs.freedesktop.org/show_bug.cgi?id=5766> Patch
#4636 <https://bugs.freedesktop.org/attachment.cgi?id=4636>
- Acknowledge that RN50 only has one CRTC, and use this to distinguish it
from RV100.
- Fix detection of RN50 memory type and bus width.
- Model RN50 memory bandwidth limits by capping the pixel clock range based
on memory clock, bpp and memory bus width. (ATI Technologies Inc.)
| -rw-r--r-- | ChangeLog | 13 | ||||
| -rw-r--r-- | src/radeon_driver.c | 20 |
2 files changed, 30 insertions, 3 deletions
@@ -1,3 +1,16 @@ +2006-03-09 Michel Dänzer <michel@daenzer.net> + + * src/radeon_driver.c: (RADEONGetClockInfo), (RADEONGetVRamType), + (RADEONPreInitConfig): + Bugzilla #5766 <https://bugs.freedesktop.org/show_bug.cgi?id=5766> + Patch #4636 <https://bugs.freedesktop.org/attachment.cgi?id=4636> + - Acknowledge that RN50 only has one CRTC, and use this to distinguish + it from RV100. + - Fix detection of RN50 memory type and bus width. + - Model RN50 memory bandwidth limits by capping the pixel clock range + based on memory clock, bpp and memory bus width. + (ATI Technologies Inc.) + 2006-03-03 Michel Dänzer <michel@daenzer.net> * man/radeon.man: diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 848b33b7..d128a1cd 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -1,5 +1,5 @@ /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v 1.117 2004/02/19 22:38:12 tsi Exp $ */ -/* $XdotOrg: driver/xf86-video-ati/src/radeon_driver.c,v 1.92 2006/03/03 16:41:41 daenzer Exp $ */ +/* $XdotOrg: driver/xf86-video-ati/src/radeon_driver.c,v 1.93 2006-03-09 06:06:24 anholt Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. @@ -1733,6 +1733,15 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) info->mclk = 200.00; } + if (info->ChipFamily == CHIP_FAMILY_RV100 && !info->HasCRTC2) { + /* Avoid RN50 corruption due to memory bandwidth starvation. + * 18 is an empirical value based on the databook and Windows driver. + */ + pll->max_pll_freq = min(pll->max_pll_freq, + 18 * info->mclk * 100 / pScrn->bitsPerPixel * + info->RamWidth / 16); + } + xf86DrvMsg (pScrn->scrnIndex, X_INFO, "PLL parameters: rf=%d rd=%d min=%ld max=%ld; xclk=%d\n", pll->reference_freq, @@ -2367,6 +2376,10 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) (info->ChipFamily == CHIP_FAMILY_RS200)){ if (tmp & RV100_HALF_MODE) info->RamWidth = 32; else info->RamWidth = 64; + if (!info->HasCRTC2) { + info->RamWidth /= 4; + info->IsDDR = TRUE; + } } else { if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128; else info->RamWidth = 64; @@ -2482,10 +2495,11 @@ static Bool RADEONPreInitConfig(ScrnInfoPtr pScrn) info->ChipFamily = CHIP_FAMILY_RV100; break; - case PCI_CHIP_RV100_QY: - case PCI_CHIP_RV100_QZ: case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ case PCI_CHIP_RN50_5969: + info->HasCRTC2 = FALSE; + case PCI_CHIP_RV100_QY: + case PCI_CHIP_RV100_QZ: info->ChipFamily = CHIP_FAMILY_RV100; /* DELL triple-head configuration. */ |