[mach64] RENDER support: save/restore, cache texture registers.

3 files changed, 78 insertions, 2 deletions

diff --git a/src/atimach64.c b/src/atimach64.c
index cc3a3cb0..401c4261 100644
--- a/src/atimach64.c
+++ b/src/atimach64.c
@@ -483,6 +483,15 @@ ATIMach64Save
         pATIHW->src_height2 = inm(SRC_HEIGHT2);
         pATIHW->src_cntl = inm(SRC_CNTL);
 
+        if (pATI->Chip >= ATI_CHIP_264GTPRO)
+        {
+            CARD32 offset = TEX_LEVEL(inm(TEX_SIZE_PITCH));
+
+            /* Save 3D control & texture registers */
+            pATIHW->tex_offset = inm(TEX_0_OFF + offset);
+            pATIHW->scale_3d_cntl = inm(SCALE_3D_CNTL);
+        }
+
         /* Save host data register */
         pATIHW->host_cntl = inm(HOST_CNTL);
 
@@ -514,6 +523,13 @@ ATIMach64Save
         /* Save context */
         pATIHW->context_mask = inm(CONTEXT_MASK);
 
+        if (pATI->Chip >= ATI_CHIP_264GTPRO)
+        {
+            /* Save texture setup registers */
+            pATIHW->tex_size_pitch = inm(TEX_SIZE_PITCH);
+            pATIHW->tex_cntl = inm(TEX_CNTL);
+        }
+
         if (pATI->Block1Base)
         {
             /* Save overlay & scaler registers */
@@ -853,6 +869,14 @@ ATIMach64Set
         outf(DST_BRES_DEC, pATIHW->dst_bres_dec);
         outf(DST_CNTL, pATIHW->dst_cntl);
 
+        if (pATI->Chip >= ATI_CHIP_264GTPRO)
+        {
+            /* Load ROP unit registers */
+            ATIMach64WaitForFIFO(pATI, 2);
+            outf(Z_CNTL, 0);
+            outf(ALPHA_TST_CNTL, 0);
+        }
+
         /* Load source registers */
         ATIMach64WaitForFIFO(pATI, 6);
         outf(SRC_OFF_PITCH, pATIHW->src_off_pitch);
@@ -865,6 +889,16 @@ ATIMach64Set
             SetWord(pATIHW->src_width2, 1) | SetWord(pATIHW->src_height2, 0));
         outf(SRC_CNTL, pATIHW->src_cntl);
 
+        if (pATI->Chip >= ATI_CHIP_264GTPRO)
+        {
+            CARD32 offset = TEX_LEVEL(pATIHW->tex_size_pitch);
+
+            /* Load 3D control & texture registers */
+            ATIMach64WaitForFIFO(pATI, 2);
+            outf(TEX_0_OFF + offset, pATIHW->tex_offset);
+            outf(SCALE_3D_CNTL, pATIHW->scale_3d_cntl);
+        }
+
         /* Load host data register */
         ATIMach64WaitForFIFO(pATI, 1);
         outf(HOST_CNTL, pATIHW->host_cntl);
@@ -912,6 +946,14 @@ ATIMach64Set
         ATIMach64WaitForFIFO(pATI, 1);
         outf(CONTEXT_MASK, pATIHW->context_mask);
 
+        if (pATI->Chip >= ATI_CHIP_264GTPRO)
+        {
+            /* Load texture setup registers */
+            ATIMach64WaitForFIFO(pATI, 2);
+            outf(TEX_SIZE_PITCH, pATIHW->tex_size_pitch);
+            outf(TEX_CNTL, pATIHW->tex_cntl);
+        }
+
         if (pATI->Block1Base)
         {
             /* Load overlay & scaler registers */
@@ -982,6 +1024,11 @@ ATIMach64Set
 
             CacheRegister(SRC_CNTL);
 
+            if (pATI->Chip >= ATI_CHIP_264GTPRO)
+            {
+                CacheRegister(SCALE_3D_CNTL);
+            }
+
             CacheRegister(HOST_CNTL);
 
             CacheRegister(PAT_REG0);
@@ -1001,6 +1048,11 @@ ATIMach64Set
             CacheRegister(CLR_CMP_MSK);
             CacheRegister(CLR_CMP_CNTL);
 
+            if (pATI->Chip >= ATI_CHIP_264GTPRO)
+            {
+                CacheRegister(TEX_SIZE_PITCH);
+            }
+
             if (pATI->Block1Base)
             {
                 CacheRegister(OVERLAY_Y_X_START);
diff --git a/src/atimach64accel.c b/src/atimach64accel.c
index b9d312e9..21e9fd72 100644
--- a/src/atimach64accel.c
+++ b/src/atimach64accel.c
@@ -151,10 +151,12 @@ ATIMach64Sync
     if ( pATI->directRenderingEnabled && pATI->NeedDRISync )
     {
 	ATIHWPtr pATIHW = &pATI->NewHW;
+	CARD32 offset;
 
 	if (pATI->OptionMMIOCache) {
 	    /* "Invalidate" the MMIO cache so the cache slots get updated */
 	    UncacheRegister(SRC_CNTL);
+	    UncacheRegister(SCALE_3D_CNTL);
 	    UncacheRegister(HOST_CNTL);
 	    UncacheRegister(PAT_CNTL);
 	    UncacheRegister(SC_LEFT_RIGHT);
@@ -165,6 +167,7 @@ ATIMach64Sync
 	    UncacheRegister(DP_PIX_WIDTH);
 	    UncacheRegister(DP_MIX);
 	    UncacheRegister(CLR_CMP_CNTL);
+	    UncacheRegister(TEX_SIZE_PITCH);
 	}
 
 	ATIDRIWaitForIdle(pATI);
@@ -185,12 +188,19 @@ ATIMach64Sync
 	outf( DP_MIX, pATIHW->dp_mix );
 	outf( DP_FRGD_CLR,  pATIHW->dp_frgd_clr );
 	outf( DP_WRITE_MASK, pATIHW->dp_write_mask );
-	
 	outf( DP_PIX_WIDTH, pATIHW->dp_pix_width );
+
 	outf( CLR_CMP_CNTL, pATIHW->clr_cmp_cntl );
+
+	offset = TEX_LEVEL(pATIHW->tex_size_pitch);
+
+	ATIMach64WaitForFIFO(pATI, 6);
 	outf( ALPHA_TST_CNTL, 0 );
 	outf( Z_CNTL, 0 );
-	outf( SCALE_3D_CNTL, 0 );
+	outf( SCALE_3D_CNTL, pATIHW->scale_3d_cntl );
+	outf( TEX_0_OFF + offset, pATIHW->tex_offset );
+	outf( TEX_SIZE_PITCH, pATIHW->tex_size_pitch );
+	outf( TEX_CNTL, pATIHW->tex_cntl );
 
 	ATIMach64WaitForFIFO(pATI, 2);
 	outf( SC_LEFT_RIGHT,
@@ -201,6 +211,7 @@ ATIMach64Sync
 	if (pATI->OptionMMIOCache) {
 	    /* Now that the cache slots reflect the register state, re-enable MMIO cache */
 	    CacheRegister(SRC_CNTL);
+	    CacheRegister(SCALE_3D_CNTL);
 	    CacheRegister(HOST_CNTL);
 	    CacheRegister(PAT_CNTL);
 	    CacheRegister(SC_LEFT_RIGHT);
@@ -211,6 +222,7 @@ ATIMach64Sync
 	    CacheRegister(DP_PIX_WIDTH);
 	    CacheRegister(DP_MIX);
 	    CacheRegister(CLR_CMP_CNTL);
+	    CacheRegister(TEX_SIZE_PITCH);
 	}
 
 	ATIMach64WaitForIdle(pATI);
@@ -288,6 +300,11 @@ TestRegisterCachingDP(ScrnInfoPtr pScreenInfo)
 
     TestRegisterCaching(SRC_CNTL);
 
+    if (pATI->Chip >= ATI_CHIP_264GTPRO)
+    {
+        TestRegisterCaching(SCALE_3D_CNTL);
+    }
+
     TestRegisterCaching(HOST_CNTL);
 
     TestRegisterCaching(PAT_REG0);
@@ -321,6 +338,11 @@ TestRegisterCachingDP(ScrnInfoPtr pScreenInfo)
     TestRegisterCaching(CLR_CMP_CLR);
     TestRegisterCaching(CLR_CMP_MSK);
     TestRegisterCaching(CLR_CMP_CNTL);
+
+    if (pATI->Chip >= ATI_CHIP_264GTPRO)
+    {
+        TestRegisterCaching(TEX_SIZE_PITCH);
+    }
 }
 
 static __inline__ void
diff --git a/src/atistruct.h b/src/atistruct.h
index 12cf61e9..08f6a5b5 100644
--- a/src/atistruct.h
+++ b/src/atistruct.h
@@ -147,6 +147,8 @@ typedef struct _ATIHWRec
     CARD32 clr_cmp_clr, clr_cmp_msk, clr_cmp_cntl;
     CARD32 context_mask, context_load_cntl;
 
+    CARD32 scale_3d_cntl, tex_size_pitch, tex_cntl, tex_offset;
+
     /* Mach64 MMIO Block 1 registers */
     CARD32 overlay_y_x_start, overlay_y_x_end, overlay_graphics_key_clr,
            overlay_graphics_key_msk, overlay_key_cntl, overlay_scale_inc,