RADEON: update RADEONGetVRAMType() for newer chips

2 files changed, 86 insertions, 18 deletions

diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index e8320e78..cb460230 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1360,16 +1360,63 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn)
     RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
     unsigned char *RADEONMMIO = info->MMIO;
     uint32_t tmp;
- 
-    if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) ||
-	(INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30))) 
+
+    if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300))
+	info->IsDDR = TRUE;
+    else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
 	info->IsDDR = TRUE;
     else
 	info->IsDDR = FALSE;
 
-    tmp = INREG(RADEON_MEM_CNTL);
-    if (IS_R300_VARIANT) {
-	tmp &=  R300_MEM_NUM_CHANNELS_MASK;
+    if ((info->ChipFamily >= CHIP_FAMILY_R600) &&
+	(info->ChipFamily <= CHIP_FAMILY_RV635)) {
+	int chansize;
+	/* r6xx */
+	tmp = INREG(R600_RAMCFG);
+	if (tmp & R600_CHANSIZE_OVERRIDE)
+	    chansize = 16;
+	else if (tmp & R600_CHANSIZE)
+	    chansize = 64;
+	else
+	    chansize = 32;
+	if (info->ChipFamily == CHIP_FAMILY_R600)
+	    info->RamWidth = 8 * chansize;
+	else if (info->ChipFamily == CHIP_FAMILY_RV670)
+	    info->RamWidth = 4 * chansize;
+	else if ((info->ChipFamily == CHIP_FAMILY_RV610) ||
+		 (info->ChipFamily == CHIP_FAMILY_RV620))
+	    info->RamWidth = chansize;
+	else if ((info->ChipFamily == CHIP_FAMILY_RV630) ||
+		 (info->ChipFamily == CHIP_FAMILY_RV635))
+	    info->RamWidth = 2 * chansize;
+    } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
+	/* rv515/rv550 */
+	tmp = INMC(pScrn, RV515_MC_CNTL);
+	tmp &= RV515_MEM_NUM_CHANNELS_MASK;
+	switch (tmp) {
+	case 0: info->RamWidth = 64; break;
+	case 1: info->RamWidth = 128; break;
+	default: info->RamWidth = 128; break;
+	}
+    } else if ((info->ChipFamily >= CHIP_FAMILY_R520) ||
+	       (info->ChipFamily <= CHIP_FAMILY_RV570)){
+	/* r520/rv530/rv560/rv570/r580 */
+	tmp = INMC(pScrn, R520_MC_CNTL0);
+	switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
+	case 0: info->RamWidth = 32; break;
+	case 1: info->RamWidth = 64; break;
+	case 2: info->RamWidth = 128; break;
+	case 3: info->RamWidth = 256; break;
+	default: info->RamWidth = 64; break;
+	}
+	if (tmp & R520_MC_CHANNEL_SIZE) {
+	    info->RamWidth *= 2;
+	}
+    } else if ((info->ChipFamily >= CHIP_FAMILY_R300) &&
+	       (info->ChipFamily <= CHIP_FAMILY_RV410)) {
+	/* r3xx, r4xx */
+	tmp = INREG(RADEON_MEM_CNTL);
+	tmp &= R300_MEM_NUM_CHANNELS_MASK;
 	switch (tmp) {
 	case 0: info->RamWidth = 64; break;
 	case 1: info->RamWidth = 128; break;
@@ -1379,15 +1426,25 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn)
     } else if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
 	       (info->ChipFamily == CHIP_FAMILY_RS100) ||
 	       (info->ChipFamily == CHIP_FAMILY_RS200)){
-	if (tmp & RV100_HALF_MODE) info->RamWidth = 32;
-	else info->RamWidth = 64;
-       if (!pRADEONEnt->HasCRTC2) {
-           info->RamWidth /= 4;
-           info->IsDDR = TRUE;
-       }
+	tmp = INREG(RADEON_MEM_CNTL);
+	if (tmp & RV100_HALF_MODE)
+	    info->RamWidth = 32;
+	else
+	    info->RamWidth = 64;
+
+	if (!pRADEONEnt->HasCRTC2) {
+	    info->RamWidth /= 4;
+	    info->IsDDR = TRUE;
+	}
+    } else if (info->ChipFamily <= CHIP_FAMILY_RV280) {
+	tmp = INREG(RADEON_MEM_CNTL);
+	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK)
+	    info->RamWidth = 128;
+	else
+	    info->RamWidth = 64;
     } else {
-	if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128;
-	else info->RamWidth = 64;
+	/* newer IGPs */
+	info->RamWidth = 128;
     }
 
     /* This may not be correct, as some cards can have half of channel disabled 
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index b2d6fd18..08bf858f 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -1069,6 +1069,7 @@
 #define RADEON_MEM_SDRAM_MODE_REG           0x0158
 #       define RADEON_SDRAM_MODE_MASK       0xffff0000
 #       define RADEON_B3MEM_RESET_MASK      0x6fffffff
+#       define RADEON_MEM_CFG_TYPE_DDR      (1 << 30)
 #define RADEON_MEM_STR_CNTL                 0x0150
 #       define RADEON_MEM_PWRUP_COMPL_A     (1 <<  0)
 #       define RADEON_MEM_PWRUP_COMPL_B     (1 <<  1)
@@ -3435,10 +3436,20 @@
 #define RV515_MC_STATUS_IDLE (1<<4)
 #define AVIVO_MC_DATA						0x0074
 
-#define RV515_MC_FB_LOCATION 0x1
-#define RV515_MC_AGP_LOCATION 0x2
-#define R520_MC_FB_LOCATION 0x4
-#define R520_MC_AGP_LOCATION 0x5
+#define RV515_MC_FB_LOCATION   0x1
+#define RV515_MC_AGP_LOCATION  0x2
+#define RV515_MC_CNTL          0x5
+#	define RV515_MEM_NUM_CHANNELS_MASK  0x3
+#define R520_MC_FB_LOCATION    0x4
+#define R520_MC_AGP_LOCATION   0x5
+#define R520_MC_CNTL0          0x8
+#	define R520_MEM_NUM_CHANNELS_MASK  (0x3 << 24)
+#	define R520_MEM_NUM_CHANNELS_SHIFT  24
+#	define R520_MC_CHANNEL_SIZE  (1 << 23)
+
+#define R600_RAMCFG				       0x2408
+#       define R600_CHANSIZE                           (1 << 7)
+#       define R600_CHANSIZE_OVERRIDE                  (1 << 10)
 
 #define AVIVO_HDP_FB_LOCATION 0x134