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authorAlex Deucher <alexdeucher@gmail.com>2009-07-08 12:33:34 -0400
committerAlex Deucher <alexdeucher@gmail.com>2009-07-08 12:33:34 -0400
commit2d86ec4ddb1fb83be95ed9cdcbabf4d568a6d7b6 (patch)
tree21cb7930ab5efdb12cd5f3dff094b32a3fce6acb
parenta68afc2a80b8581cc3d67e9b5a95a10b0d4ead0e (diff)
Fix the build for the !XF86DRM_MODE case
compile tested only.
-rw-r--r--src/radeon.h25
-rw-r--r--src/radeon_exa_funcs.c12
-rw-r--r--src/radeon_exa_render.c6
3 files changed, 39 insertions, 4 deletions
diff --git a/src/radeon.h b/src/radeon.h
index d4e89d47..c5b2cc27 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1537,7 +1537,7 @@ do { \
} \
info->accel_state->engineMode = EXA_ENGINEMODE_2D; \
} while (0);
-
+# ifdef XF86DRM_MODE
#define RADEON_SWITCH_TO_3D() \
do { \
uint32_t flush = 0; \
@@ -1560,6 +1560,29 @@ do { \
RADEONInit3DEngine(pScrn); \
info->accel_state->engineMode = EXA_ENGINEMODE_3D; \
} while (0);
+# else
+#define RADEON_SWITCH_TO_3D() \
+do { \
+ uint32_t flush = 0; \
+ switch (info->accel_state->engineMode) { \
+ case EXA_ENGINEMODE_UNKNOWN: \
+ case EXA_ENGINEMODE_2D: \
+ flush = 1; \
+ break; \
+ case EXA_ENGINEMODE_3D: \
+ break; \
+ } \
+ if (flush) { \
+ if (info->cs) \
+ radeon_cs_flush_indirect(pScrn); \
+ else if (info->directRenderingEnabled) \
+ RADEONCPFlushIndirect(pScrn, 1); \
+ } \
+ if (!info->accel_state->XInited3D) \
+ RADEONInit3DEngine(pScrn); \
+ info->accel_state->engineMode = EXA_ENGINEMODE_3D; \
+} while (0);
+# endif
#else
#define RADEON_SWITCH_TO_2D()
#define RADEON_SWITCH_TO_3D()
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index d2152287..4b75299d 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -218,7 +218,11 @@ FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2)
TRACE;
#ifdef ACCEL_CP
- if (info->cs && info->cs->cdw > 15 * 1024) {
+ if (info->cs
+#ifdef XF86DRM_MODE
+ && info->cs->cdw > 15 * 1024
+#endif
+ ) {
FUNC_NAME(RADEONDone2D)(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
FUNC_NAME(Emit2DState)(pScrn, RADEON_2D_EXA_SOLID);
@@ -327,7 +331,11 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst,
TRACE;
#ifdef ACCEL_CP
- if (info->cs && info->cs->cdw > 15 * 1024) {
+ if (info->cs
+#ifdef XF86DRM_MODE
+ && info->cs->cdw > 15 * 1024
+#endif
+ ) {
FUNC_NAME(RADEONDone2D)(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
FUNC_NAME(Emit2DState)(pScrn, RADEON_2D_EXA_COPY);
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 10144a60..73f8ee94 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -2116,7 +2116,11 @@ static void FUNC_NAME(RadeonCompositeTile)(ScrnInfoPtr pScrn,
srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
#ifdef ACCEL_CP
- if (info->cs && info->cs->cdw > 15 * 1024) {
+ if (info->cs
+#ifdef XF86DRM_MODE
+ && info->cs->cdw > 15 * 1024
+#endif
+ ) {
FUNC_NAME(RadeonDoneComposite)(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
info->accel_state->exa->PrepareComposite(info->accel_state->composite_op,