diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2008-08-14 14:49:45 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2008-08-14 14:49:45 -0400 |
| commit | 92ee21df344a989778e37369c7beb3904a00ead6 (patch) | |
| tree | 614c1163751f139fbb4e881889550dbffce8d0ca | |
| parent | 0d5e0347af4322713075193154b8a348de4a0b52 (diff) | |
PLL adjustments
Seems higher dotclocks prefer a higher FB div.
Someone with a lot of should try and find out where
the div sweet spots are for various dotclock ranges.
fixes bug 17125
| -rw-r--r-- | src/atombios_crtc.c | 6 | ||||
| -rw-r--r-- | src/legacy_crtc.c | 7 | ||||
| -rw-r--r-- | src/radeon.h | 7 | ||||
| -rw-r--r-- | src/radeon_crtc.c | 7 |
4 files changed, 23 insertions, 4 deletions
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c index 70650e12..8f5b40ae 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -225,7 +225,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) if (IS_AVIVO_VARIANT) { uint32_t temp; - pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; + if (mode->Clock > 120000) /* range limits??? */ + pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; + else + pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; + RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, pll_flags); sclock = temp; diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c index 334194a5..8995679f 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c @@ -1705,10 +1705,15 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, RADEONInfoPtr info = RADEONPTR(pScrn); int i = 0; double dot_clock = 0; - int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV; + int pll_flags = RADEON_PLL_LEGACY; Bool update_tv_routing = FALSE; Bool tilingChanged = FALSE; + if (adjusted_mode->Clock > 120000) /* range limits??? */ + pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; + else + pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; + if (info->allowColorTiling) { radeon_crtc->can_tile = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; tilingChanged = RADEONSetTiling(pScrn); diff --git a/src/radeon.h b/src/radeon.h index 975e5d10..2348e7ce 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -250,7 +250,12 @@ typedef struct { #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) #define RADEON_PLL_USE_REF_DIV (1 << 2) #define RADEON_PLL_LEGACY (1 << 3) -#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) +#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) +#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) +#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) +#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) +#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) +#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) typedef struct { uint16_t reference_freq; diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index 13166698..5ab00c1f 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -228,7 +228,12 @@ RADEONComputePLL(RADEONPLLPtr pll, best_freq = current_freq; best_error = error; best_vco_diff = vco_diff; - } else if ((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) { + } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || + ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || + ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || + ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || + ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || + ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { best_post_div = post_div; best_ref_div = ref_div; best_feedback_div = feedback_div; |