diff options
| author | Qiang Yu <Qiang.Yu@amd.com> | 2016-04-11 16:35:37 +0900 |
|---|---|---|
| committer | Michel Dänzer <michel.daenzer@amd.com> | 2016-04-11 16:35:37 +0900 |
| commit | ba8b6288c8e6fc4be5d7144ecbe9a1f241881674 (patch) | |
| tree | 495c8c8680d1ac4746b92aa8a24b88b0c741ff83 | |
| parent | bd4c72c8625996d842824ce4963f2d759fe2954a (diff) | |
Remove RR_Capability_SinkOutput for GPU without CRTC
Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
(Ported from amdgpu commit a0bbb373f902e0ffc14570c85faec7e44134f62e)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | src/radeon_kms.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/radeon_kms.c b/src/radeon_kms.c index c5310eaa..c35c9510 100644 --- a/src/radeon_kms.c +++ b/src/radeon_kms.c @@ -1108,8 +1108,11 @@ static void RADEONSetupCapabilities(ScrnInfoPtr pScrn) if (ret == 0) { if (value & DRM_PRIME_CAP_EXPORT) pScrn->capabilities |= RR_Capability_SourceOutput | RR_Capability_SinkOffload; - if (value & DRM_PRIME_CAP_IMPORT) - pScrn->capabilities |= RR_Capability_SinkOutput | RR_Capability_SourceOffload; + if (value & DRM_PRIME_CAP_IMPORT) { + pScrn->capabilities |= RR_Capability_SourceOffload; + if (info->drmmode.count_crtcs) + pScrn->capabilities |= RR_Capability_SinkOutput; + } } #endif } @@ -1228,8 +1231,6 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) info->allowColorTiling2D = FALSE; - RADEONSetupCapabilities(pScrn); - /* don't enable tiling if accel is not enabled */ if (!info->r600_shadow_fb) { Bool colorTilingDefault = @@ -1328,6 +1329,8 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) goto fail; } + RADEONSetupCapabilities(pScrn); + if (info->drmmode.count_crtcs == 1) pRADEONEnt->HasCRTC2 = FALSE; else |