Fix indentation on IS_R300_3D Xv code.

1 files changed, 61 insertions, 68 deletions

diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 3292ccad..855bf163 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -343,13 +343,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 
 	/* setup pixel shader */
 	if (IS_R300_3D) {
-	if (pPriv->bicubic_enabled) {
+	    if (pPriv->bicubic_enabled) {
 		BEGIN_ACCEL(79);
 
 		/* 4 components: 2 for tex0 and 2 for tex1 */
-		OUT_ACCEL_REG(R300_RS_COUNT,
-			  ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
-			   R300_RS_COUNT_HIRES_EN));
+		OUT_ACCEL_REG(R300_RS_COUNT, ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+						   R300_RS_COUNT_HIRES_EN));
 
 		/* R300_INST_COUNT_RS - highest RS instruction used */
 		OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
@@ -682,73 +681,67 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 		OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), 0);
 
 		FINISH_ACCEL();
-		} else {
+	    } else {
 		BEGIN_ACCEL(8);
-	    /* 2 components: 2 for tex0 */
-	    OUT_ACCEL_REG(R300_RS_COUNT,
+		/* 2 components: 2 for tex0 */
+		OUT_ACCEL_REG(R300_RS_COUNT,
 			  ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
 			   R300_RS_COUNT_HIRES_EN));
-	    /* R300_INST_COUNT_RS - highest RS instruction used */
-	    OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
-
-	    OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */
-
-	    OUT_ACCEL_REG(R300_US_CODE_OFFSET,
-			  (R300_ALU_CODE_OFFSET(0) |
-			   R300_ALU_CODE_SIZE(1) |
-			   R300_TEX_CODE_OFFSET(0) |
-			   R300_TEX_CODE_SIZE(1)));
-
-	    OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0) |
-			   R300_RGBA_OUT));
-
-	    /* tex inst is preloaded in RADEONInit3DEngine() */
-
-	    /* ALU inst */
-	    /* RGB */
-	    OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0,
-			  (R300_ALU_RGB_ADDR0(0) |
-			   R300_ALU_RGB_ADDR1(0) |
-			   R300_ALU_RGB_ADDR2(0) |
-			   R300_ALU_RGB_ADDRD(0) |
-			   R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R |
-					       R300_ALU_RGB_MASK_G |
-					       R300_ALU_RGB_MASK_B)) |
-			   R300_ALU_RGB_TARGET_A));
-	    OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0,
-			  (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
-			   R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
-			   R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
-			   R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
-			   R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
-			   R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
-			   R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
-			   R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
-			   R300_ALU_RGB_CLAMP));
-	    /* Alpha */
-	    OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0,
-			  (R300_ALU_ALPHA_ADDR0(0) |
-			   R300_ALU_ALPHA_ADDR1(0) |
-			   R300_ALU_ALPHA_ADDR2(0) |
-			   R300_ALU_ALPHA_ADDRD(0) |
-			   R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
-			   R300_ALU_ALPHA_TARGET_A |
-			   R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
-	    OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0,
-			  (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) |
-			   R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
-			   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) |
-			   R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) |
-			   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
-			   R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
-			   R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
-			   R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
-			   R300_ALU_ALPHA_CLAMP));
-	    FINISH_ACCEL();
+		/* R300_INST_COUNT_RS - highest RS instruction used */
+		OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+
+		OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */
+
+		OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+						   R300_ALU_CODE_SIZE(1) |
+						   R300_TEX_CODE_OFFSET(0) |
+						   R300_TEX_CODE_SIZE(1)));
+
+		OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) |
+						   R300_ALU_SIZE(0) |
+						   R300_TEX_START(0) |
+						   R300_TEX_SIZE(0) |
+						   R300_RGBA_OUT));
+
+		/* tex inst is preloaded in RADEONInit3DEngine() */
+
+		/* ALU inst */
+		/* RGB */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, (R300_ALU_RGB_ADDR0(0) |
+						   R300_ALU_RGB_ADDR1(0) |
+						   R300_ALU_RGB_ADDR2(0) |
+						   R300_ALU_RGB_ADDRD(0) |
+						   R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R |
+						   R300_ALU_RGB_MASK_G |
+						   R300_ALU_RGB_MASK_B)) |
+						   R300_ALU_RGB_TARGET_A));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+						   R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+						   R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
+						   R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
+						   R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
+						   R300_ALU_RGB_CLAMP));
+		/* Alpha */
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, (R300_ALU_ALPHA_ADDR0(0) |
+						   R300_ALU_ALPHA_ADDR1(0) |
+						   R300_ALU_ALPHA_ADDR2(0) |
+						   R300_ALU_ALPHA_ADDRD(0) |
+						   R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
+						   R300_ALU_ALPHA_TARGET_A |
+						   R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) |
+						   R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) |
+						   R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
+						   R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
+						   R300_ALU_ALPHA_CLAMP));
+		FINISH_ACCEL();
 		}
 	} else {
 	    if (pPriv->bicubic_enabled) {