Add r3xx-specific bicubic filtering code. FP, RS, mostly, everything else is shared with r5xx.

1 files changed, 381 insertions, 1 deletions

diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index c5ad0e18..8fb87981 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -90,6 +90,45 @@ do {								\
 
 #endif /* !ACCEL_CP */
 
+#ifndef __FLOAT_TO_S16E7__
+#define __FLOAT_TO_S16E7__
+
+static int float_to_s16e7(float in)
+{
+	union {
+		float f;
+		int i;
+	} x;
+
+	int s, e, f, out; // sign, exponent, fraction
+
+	x.f = in;
+	s = (x.i & (1 << 31)) >> 31;
+	e = (x.i & 0x7f800000) >> 23;
+	f = (x.i & 0x007fffff);
+
+	/* unbias the exponent */
+	e = e - 127;
+	if (e < -63)
+		e = -63;
+	else if (e > 63)
+		e = 63;
+
+	e += 63;
+
+	/* prepend implicit 1 to fraction */
+	f |= (1 << 23);
+	/* cut mantissa to 16 bits */
+	f = (f & 0xffff80) >> 8;
+
+	out = s;
+	out = (out << 7) | e;
+	out = (out << 16) | f;
+
+	return out;
+}
+#endif
+
 static void
 FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
 {
@@ -343,7 +382,347 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 
 	/* setup pixel shader */
 	if (IS_R300_3D) {
-	    BEGIN_ACCEL(9);
+	if (pPriv->bicubic_enabled) {
+		BEGIN_ACCEL(79);
+
+		/* 4 components: 2 for tex0 and 2 for tex1 */
+		OUT_ACCEL_REG(R300_RS_COUNT,
+			  ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+			   R300_RS_COUNT_HIRES_EN));
+
+		/* R300_INST_COUNT_RS - highest RS instruction used */
+		OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+
+		/* Pixel stack frame size. */
+		OUT_ACCEL_REG(R300_US_PIXSIZE, 5);
+
+		/* Indirection levels */
+		OUT_ACCEL_REG(R300_US_CONFIG, ((2 << R300_NLEVEL_SHIFT) |
+							R300_FIRST_TEX));
+
+		/* Set nodes. */
+		OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+							R300_ALU_CODE_SIZE(14) |
+							R300_TEX_CODE_OFFSET(0) |
+							R300_TEX_CODE_SIZE(6)));
+
+		OUT_ACCEL_REG(R300_US_CODE_ADDR_3, (R300_ALU_START(0) |
+							R300_ALU_SIZE(1) |
+							R300_TEX_START(0) |
+							R300_TEX_SIZE(1)));
+		OUT_ACCEL_REG(R300_US_CODE_ADDR_2, (R300_ALU_START(1) |
+							R300_ALU_SIZE(10) |
+							R300_TEX_START(1) |
+							R300_TEX_SIZE(1)));
+		OUT_ACCEL_REG(R300_US_CODE_ADDR_1, (R300_ALU_START(11) |
+							R300_ALU_SIZE(3) |
+							R300_TEX_START(2) |
+							R300_TEX_SIZE(4) |
+							R300_RGBA_OUT));
+		OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0);
+
+		/* ** BICUBIC FP ** */
+
+		/* texcoord0 => temp0
+		 * texcoord1 => temp1 */
+
+		// first node
+		/* TEX temp2, temp1.rrr0, tex1, 1D */
+		OUT_ACCEL_REG(R300_US_TEX_INST(0), (R300_TEX_INST(R300_TEX_INST_LD) |
+						   R300_TEX_ID(1) |
+						   R300_TEX_SRC_ADDR(1) |
+						   R300_TEX_DST_ADDR(2)));
+
+		/* MAD temp1.r, temp1.ggg0, 1.0, 0.0 */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0), (R300_ALU_RGB_ADDR0(1) |
+						   R300_ALU_RGB_ADDRD(1) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0), (R300_ALU_ALPHA_ADDRD(1) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+
+		// second node
+		/* TEX temp1, temp1, tex1, 1D */
+		OUT_ACCEL_REG(R300_US_TEX_INST(1), (R300_TEX_INST(R300_TEX_INST_LD) |
+						   R300_TEX_ID(1) |
+						   R300_TEX_SRC_ADDR(1) |
+						   R300_TEX_DST_ADDR(1)));
+
+		/* MAD temp3.rg, temp2.ggg0, const0.rgb0, 0.0 */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(1), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(1), (R300_ALU_RGB_ADDR0(2) |
+						   R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(0)) |
+						   R300_ALU_RGB_ADDRD(3) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(1), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(3) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+		
+
+		/* MAD temp2.rg, temp2.rrr0, const0.rgb, 0.0 */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(2), (R300_ALU_RGB_ADDR0(2) |
+						   R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(0)) |
+						   R300_ALU_RGB_ADDRD(2) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(2), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(2), (R300_ALU_ALPHA_ADDRD(2) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+		/* MAD temp4.rg, temp1.ggg0, const1.rgb, temp3.rgb0 */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(3), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(3), (R300_ALU_RGB_ADDR0(1) |
+						   R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
+						   R300_ALU_RGB_ADDR2(3) |
+						   R300_ALU_RGB_ADDRD(4) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(3), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(3), (R300_ALU_ALPHA_ADDRD(4) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+		/* MAD temp5.rg, temp1.ggg0, const1.rgb, temp2.rgb0 */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(4), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_GGG) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(4), (R300_ALU_RGB_ADDR0(1) |
+						   R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
+						   R300_ALU_RGB_ADDR2(2) |
+						   R300_ALU_RGB_ADDRD(5) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(4), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(4), (R300_ALU_ALPHA_ADDRD(5) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+		/* MAD temp3.rg, temp1.rrr0, const1.rgb, temp3.rgb0 */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(5), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(5), (R300_ALU_RGB_ADDR0(1) |
+						   R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
+						   R300_ALU_RGB_ADDR2(3) |
+						   R300_ALU_RGB_ADDRD(3) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(5), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(5), (R300_ALU_ALPHA_ADDRD(3) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+		/* MAD temp1.rg, temp1.rrr0, const1.rgb, temp2.rgb0 */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(6), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RRR) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRC1_RGB) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(6), (R300_ALU_RGB_ADDR0(1) |
+						   R300_ALU_RGB_ADDR1(R300_ALU_RGB_CONST(1)) |
+						   R300_ALU_RGB_ADDR2(2) |
+						   R300_ALU_RGB_ADDRD(1) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(6), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(6), (R300_ALU_ALPHA_ADDRD(1) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+		/* MAD temp1.rg, temp0.rgb0, 1.0, temp1.rgb0 */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(7), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(7), (R300_ALU_RGB_ADDR0(0) |
+						   R300_ALU_RGB_ADDR2(1) |
+						   R300_ALU_RGB_ADDRD(1) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(7), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(7), (R300_ALU_ALPHA_ADDRD(1) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+		/* MAD temp2.rg, temp0.rgb0, 1.0, temp3.rgb0 */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(8), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(8), (R300_ALU_RGB_ADDR0(0) |
+						   R300_ALU_RGB_ADDR2(3) |
+						   R300_ALU_RGB_ADDRD(2) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(8), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(8), (R300_ALU_ALPHA_ADDRD(2) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+		/* MAD temp3.rg, temp0.rgb0, 1.0, temp5.rgb0 */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(9), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(9), (R300_ALU_RGB_ADDR0(0) |
+						   R300_ALU_RGB_ADDR2(5) |
+						   R300_ALU_RGB_ADDRD(3) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(9), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(9), (R300_ALU_ALPHA_ADDRD(3) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+		/* MAD temp0.rg, temp0.rgb0, 1.0, temp4.rgb0 */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(10), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC2_RGB)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(10), (R300_ALU_RGB_ADDR0(0) |
+						   R300_ALU_RGB_ADDR2(4) |
+						   R300_ALU_RGB_ADDRD(0) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_R | R300_ALU_RGB_MASK_G)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(10), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_0_0) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(10), (R300_ALU_ALPHA_ADDRD(0) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
+
+
+		// third node
+		/* TEX temp4, temp1.rg--, tex0, 1D */
+		OUT_ACCEL_REG(R300_US_TEX_INST(2), (R300_TEX_INST(R300_TEX_INST_LD) |
+						   R300_TEX_ID(0) |
+						   R300_TEX_SRC_ADDR(1) |
+						   R300_TEX_DST_ADDR(4)));
+
+		/* TEX temp3, temp3.rg--, tex0, 1D */
+		OUT_ACCEL_REG(R300_US_TEX_INST(3), (R300_TEX_INST(R300_TEX_INST_LD) |
+						   R300_TEX_ID(0) |
+						   R300_TEX_SRC_ADDR(3) |
+						   R300_TEX_DST_ADDR(3)));
+
+		/* TEX temp5, temp2.rg--, tex0, 1D */
+		OUT_ACCEL_REG(R300_US_TEX_INST(4), (R300_TEX_INST(R300_TEX_INST_LD) |
+						   R300_TEX_ID(0) |
+						   R300_TEX_SRC_ADDR(2) |
+						   R300_TEX_DST_ADDR(5)));
+
+		/* TEX temp0, temp0.rg--, tex0, 1D */
+		OUT_ACCEL_REG(R300_US_TEX_INST(5), (R300_TEX_INST(R300_TEX_INST_LD) |
+						   R300_TEX_ID(0) |
+						   R300_TEX_SRC_ADDR(0) |
+						   R300_TEX_DST_ADDR(0)));
+
+		/* MAD temp3.rgba, temp1.bbbb, srcp(temp4.rgba - temp3.rgba), temp3.rgba */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(11), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) |
+						   R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(11), (R300_ALU_RGB_ADDR0(3) |
+						   R300_ALU_RGB_ADDR1(4) |
+						   R300_ALU_RGB_ADDR2(1) |
+						   R300_ALU_RGB_ADDRD(3) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(11), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(11), (R300_ALU_ALPHA_ADDR0(3) |
+						   R300_ALU_ALPHA_ADDR1(4) |
+						   R300_ALU_ALPHA_ADDR2(1) |
+						   R300_ALU_ALPHA_ADDRD(3) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A)));
+
+		/* MAD temp0.rgba, temp1.bbbb, srcp(temp5.rgba - temp0.rgba), temp0.rgba   NOP*/
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(12), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) |
+						   R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0) |
+						   R300_ALU_RGB_INSERT_NOP));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(12), (R300_ALU_RGB_ADDR0(0) |
+						   R300_ALU_RGB_ADDR1(5) |
+						   R300_ALU_RGB_ADDR2(1) |
+						   R300_ALU_RGB_ADDRD(0) |
+						   R300_ALU_RGB_WMASK(R300_ALU_RGB_MASK_RGB)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(12), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(12), (R300_ALU_ALPHA_ADDR0(0) |
+						   R300_ALU_ALPHA_ADDR1(5) |
+						   R300_ALU_ALPHA_ADDR2(1) |
+						   R300_ALU_ALPHA_ADDRD(0) |
+						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A)));
+
+		/* MAD output, temp2.bbbb, srcp(temp3.rgba - temp0.rgba), temp0.rgba */
+		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(13), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+						   R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC2_BBB) |
+						   R300_ALU_RGB_SEL_B(R300_ALU_RGB_SRCP_RGB) |
+						   R300_ALU_RGB_SEL_C(R300_ALU_RGB_SRC0_RGB) |
+						   R300_ALU_RGB_SRCP_OP(R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0)));
+		OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(13), (R300_ALU_RGB_ADDR0(0) |
+						   R300_ALU_RGB_ADDR1(3) |
+						   R300_ALU_RGB_ADDR2(2) |
+						   R300_ALU_RGB_OMASK(R300_ALU_RGB_MASK_RGB)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(13), (R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+						   R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC2_B) |
+						   R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_SRCP_A) |
+						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_SRC0_A)));
+		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(13), (R300_ALU_ALPHA_ADDR0(0) |
+						   R300_ALU_ALPHA_ADDR1(3) |
+						   R300_ALU_ALPHA_ADDR2(2) |
+						   R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A)));
+
+		/* Shader constants. */
+		OUT_ACCEL_REG(R300_US_ALU_CONST_R(0), float_to_s16e7(1.0/(float)pPriv->w));
+		OUT_ACCEL_REG(R300_US_ALU_CONST_G(0), 0);
+		OUT_ACCEL_REG(R300_US_ALU_CONST_B(0), 0);
+		OUT_ACCEL_REG(R300_US_ALU_CONST_A(0), 0);
+
+		OUT_ACCEL_REG(R300_US_ALU_CONST_R(1), 0);
+		OUT_ACCEL_REG(R300_US_ALU_CONST_G(1), float_to_s16e7(1.0/(float)pPriv->h));
+		OUT_ACCEL_REG(R300_US_ALU_CONST_B(1), 0);
+		OUT_ACCEL_REG(R300_US_ALU_CONST_A(1), 0);
+
+		FINISH_VIDEO();
+		} else {
+		BEGIN_VIDEO(8);
 	    /* 2 components: 2 for tex0 */
 	    OUT_ACCEL_REG(R300_RS_COUNT,
 			  ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -409,6 +788,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 			   R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
 			   R300_ALU_ALPHA_CLAMP));
 	    FINISH_ACCEL();
+		}
 	} else {
 	    if (pPriv->bicubic_enabled) {
 		BEGIN_ACCEL(7);