diff options
| author | Eric Anholt <anholt@freebsd.org> | 2006-04-28 02:55:08 +0000 |
|---|---|---|
| committer | Eric Anholt <anholt@freebsd.org> | 2006-04-28 02:55:08 +0000 |
| commit | eb841974d041b19461b7fb726687df8938b2e39b (patch) | |
| tree | cb000a6cfcfa55e2145b2d4c406667fa493fa654 | |
| parent | 85e2ee6de6fd347aad66785ec7119f92013cd994 (diff) | |
Bug #6761: Fix font rendering in non-DRI mode by replacing RB2D_DSTCACHE_*
with RB3D_DSTCACHE_*. The RB2D versions are read-only mirrors of the
RB3D. This is masked when DRI is enabled because the DRM uses the right
registers in its flushing.
| -rw-r--r-- | ChangeLog | 10 | ||||
| -rw-r--r-- | src/radeon_accel.c | 14 |
2 files changed, 17 insertions, 7 deletions
@@ -1,3 +1,13 @@ +2006-04-27 Eric Anholt <anholt@FreeBSD.org> + + reviewed by: Michel Dänzer <michel@daenzer.net> + + * src/radeon_accel.c: (RADEONEngineFlush), (RADEONEngineReset): + Bug #6761: Fix font rendering in non-DRI mode by replacing + RB2D_DSTCACHE_* with RB3D_DSTCACHE_*. The RB2D versions are read-only + mirrors of the RB3D. This is masked when DRI is enabled because the DRM + uses the right registers in its flushing. + 2006-04-26 Dave Airlie <airlied@linux.ie> * src/radeon.h: diff --git a/src/radeon_accel.c b/src/radeon_accel.c index d3a52a48..0de3551d 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -156,16 +156,16 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn) unsigned char *RADEONMMIO = info->MMIO; int i; - OUTREGP(RADEON_RB2D_DSTCACHE_CTLSTAT, - RADEON_RB2D_DC_FLUSH_ALL, - ~RADEON_RB2D_DC_FLUSH_ALL); + OUTREGP(RADEON_RB3D_DSTCACHE_CTLSTAT, + RADEON_RB3D_DC_FLUSH_ALL, + ~RADEON_RB3D_DC_FLUSH_ALL); for (i = 0; i < RADEON_TIMEOUT; i++) { - if (!(INREG(RADEON_RB2D_DSTCACHE_CTLSTAT) & RADEON_RB2D_DC_BUSY)) + if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY)) break; } if (i == RADEON_TIMEOUT) { RADEONTRACE(("DC flush timeout: %x\n", - INREG(RADEON_RB2D_DSTCACHE_CTLSTAT))); + INREG(RADEON_RB3D_DSTCACHE_CTLSTAT))); } } @@ -256,8 +256,8 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) RADEON_SOFT_RESET_E2)); INREG(RADEON_RBBM_SOFT_RESET); OUTREG(RADEON_RBBM_SOFT_RESET, 0); - tmp = INREG(RADEON_RB2D_DSTCACHE_MODE); - OUTREG(RADEON_RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */ + tmp = INREG(RADEON_RB3D_DSTCACHE_MODE); + OUTREG(RADEON_RB3D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */ } else { OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | RADEON_SOFT_RESET_CP | |