Merge branch 'master' of git://anongit.freedesktop.org/xorg/driver/xf86-video-ati

17 files changed, 222 insertions, 79 deletions

diff --git a/configure.ac b/configure.ac
index 74185581..9ac46f73 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
 
 AC_PREREQ(2.57)
 AC_INIT([xf86-video-ati],
-        6.8.191,
+        6.8.192,
         [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
         xf86-video-ati)
 
@@ -244,6 +244,64 @@ if test "x$XSERVER_LIBPCIACCESS" = xyes; then
 fi
 AM_CONDITIONAL(XSERVER_LIBPCIACCESS, test "x$XSERVER_LIBPCIACCESS" = xyes)
 
+# Checks for headers/macros for byte swapping
+# Known variants:
+#	<byteswap.h> bswap_16, bswap_32, bswap_64  (glibc)
+#	<sys/endian.h> __swap16, __swap32, __swap64 (OpenBSD)
+#	<sys/endian.h> bswap16, bswap32, bswap64 (other BSD's)
+#	and a fallback to local macros if none of the above are found
+
+# if <byteswap.h> is found, assume it's the correct version
+AC_CHECK_HEADERS([byteswap.h])
+
+# if <sys/endian.h> is found, have to check which version
+AC_CHECK_HEADER([sys/endian.h], [HAVE_SYS_ENDIAN_H="yes"], [HAVE_SYS_ENDIAN_H="no"])
+
+if test "x$HAVE_SYS_ENDIAN_H" = "xyes" ; then
+	AC_MSG_CHECKING([for __swap16 variant of <sys/endian.h> byteswapping macros])
+	AC_LINK_IFELSE([AC_LANG_PROGRAM([
+#include <sys/endian.h>
+ ], [
+int a = 1, b;
+b = __swap16(a);
+ ])
+], [SYS_ENDIAN__SWAP='yes'], [SYS_ENDIAN__SWAP='no'])
+	AC_MSG_RESULT([$SYS_ENDIAN__SWAP])
+
+	AC_MSG_CHECKING([for bswap16 variant of <sys/endian.h> byteswapping macros])
+	AC_LINK_IFELSE([AC_LANG_PROGRAM([
+#include <sys/endian.h>
+ ], [
+int a = 1, b;
+b = bswap16(a);
+ ])
+], [SYS_ENDIAN_BSWAP='yes'], [SYS_ENDIAN_BSWAP='no'])
+	AC_MSG_RESULT([$SYS_ENDIAN_BSWAP])
+
+    	if test "$SYS_ENDIAN_BSWAP" = "yes" ; then
+		USE_SYS_ENDIAN_H=yes
+		BSWAP=bswap
+	else	
+	    	if test "$SYS_ENDIAN__SWAP" = "yes" ; then
+			USE_SYS_ENDIAN_H=yes
+			BSWAP=__swap
+		else
+			USE_SYS_ENDIAN_H=no
+		fi
+	fi
+
+	if test "$USE_SYS_ENDIAN_H" = "yes" ; then
+	    AC_DEFINE([USE_SYS_ENDIAN_H], 1, 
+		[Define to use byteswap macros from <sys/endian.h>])
+	    AC_DEFINE_UNQUOTED([bswap_16], ${BSWAP}16, 
+			[Define to 16-bit byteswap macro])
+	    AC_DEFINE_UNQUOTED([bswap_32], ${BSWAP}32, 
+			[Define to 32-bit byteswap macro])
+	    AC_DEFINE_UNQUOTED([bswap_64], ${BSWAP}64, 
+			[Define to 64-bit byteswap macro])
+	fi
+fi
+
 case $host_os in
   *linux*)
   AC_DEFINE(FGL_LINUX, 1, [Use linux pragma pack]) ;;
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index eee1d60d..a740df8d 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -173,6 +173,7 @@
 #define PCI_CHIP_RV410_564F 0x564F
 #define PCI_CHIP_RV410_5652 0x5652
 #define PCI_CHIP_RV410_5653 0x5653
+#define PCI_CHIP_RV410_5657 0x5657
 #define PCI_CHIP_MACH64VT 0x5654
 #define PCI_CHIP_MACH64VU 0x5655
 #define PCI_CHIP_MACH64VV 0x5656
@@ -195,7 +196,6 @@
 #define PCI_CHIP_RV370_5B60 0x5B60
 #define PCI_CHIP_RV370_5B62 0x5B62
 #define PCI_CHIP_RV370_5B63 0x5B63
-#define PCI_CHIP_RV370_5657 0x5657
 #define PCI_CHIP_RV370_5B64 0x5B64
 #define PCI_CHIP_RV370_5B65 0x5B65
 #define PCI_CHIP_RV280_5C61 0x5C61
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index b5b7ca8c..363addfe 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -185,8 +185,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags)
     if (IS_AVIVO_VARIANT) {
 	uint32_t temp;
 
-	if (IS_DCE3_VARIANT)
-	    pll_flags |= RADEON_PLL_DCE3;
+	pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 
 	RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, pll_flags);
 	sclock = temp;
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index 590a445d..3df61a7a 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -636,10 +636,9 @@ void
 legacy_crtc_dpms(xf86CrtcPtr crtc, int mode)
 {
     int mask;
-    ScrnInfoPtr pScrn = crtc->scrn;
     RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-    RADEONInfoPtr info = RADEONPTR(pScrn);
-    unsigned char *RADEONMMIO = info->MMIO;
+    RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
+    unsigned char *RADEONMMIO = pRADEONEnt->MMIO;
 
     mask = radeon_crtc->crtc_id ? (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) : (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS);
 
@@ -1730,7 +1729,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
     RADEONInfoPtr info = RADEONPTR(pScrn);
     int i = 0;
     double dot_clock = 0;
-    int pll_flags = RADEON_PLL_LEGACY;
+    int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV;
     Bool update_tv_routing = FALSE;
     Bool tilingChanged = FALSE;
 
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 4df81abd..9c9ebb9f 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -727,6 +727,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
 		    save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
 		}
 		tv_dac_change = 1;
+		/* IGP chips seem to use a mix of Primary and TVDAC controls */
+		if (info->IsIGP) {
+		    tmp = INREG(RADEON_CRTC_EXT_CNTL);
+		    tmp |= RADEON_CRTC_CRT_ON;
+		    OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+		    save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
+		    RADEONDacPowerSet(pScrn, bEnable, TRUE);
+		}
 	    }
 	} else if (radeon_output->MonType == MT_DFP) {
 	    if (radeon_output->TMDSType == TMDS_INT) {
@@ -807,6 +815,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
 			save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
 		    }
 		}
+		/* IGP chips seem to use a mix of Primary and TVDAC controls */
+		if (info->IsIGP) {
+		    tmp = INREG(RADEON_CRTC_EXT_CNTL);
+		    tmp &= ~RADEON_CRTC_CRT_ON;
+		    OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+		    save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
+		    RADEONDacPowerSet(pScrn, bEnable, TRUE);
+		}
 	    }
 	} else if (radeon_output->MonType == MT_DFP) {
 	    if (radeon_output->TMDSType == TMDS_INT) {
@@ -1367,6 +1383,7 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
 {
     Bool IsPrimary = crtc_num == 0 ? TRUE : FALSE;
     RADEONOutputPrivatePtr radeon_output = output->driver_private;
+    RADEONInfoPtr info = RADEONPTR(pScrn);
 
     if (crtc_num == 0)
 	RADEONInitRMXRegisters(output, save, mode);
@@ -1376,6 +1393,9 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
 	    RADEONInitDACRegisters(output, save, mode, IsPrimary);
 	} else {
 	    RADEONInitDAC2Registers(output, save, mode, IsPrimary);
+	    /* IGP chips seem to use a mix of primary and TVDAC controls */
+	    if (info->IsIGP)
+		RADEONInitDACRegisters(output, save, mode, IsPrimary);
 	}
     } else if (radeon_output->MonType == MT_LCD) {
 	RADEONInitLVDSRegisters(output, save, mode, IsPrimary);
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 9e19275c..1f6fa825 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -174,6 +174,7 @@
 "0x564F","RV410_564F","RV410",1,,,,,"ATI Mobility Radeon X700 XL (M26) (PCIE)"
 "0x5652","RV410_5652","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)"
 "0x5653","RV410_5653","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)"
+"0x5657","RV410_5657","RV410",,,,,,"ATI Radeon X550XTX 5657 (PCIE)"
 "0x5654","MACH64VT","MACH64",,,,,,
 "0x5655","MACH64VU","MACH64",,,,,,
 "0x5656","MACH64VV","MACH64",,,,,,
@@ -196,7 +197,6 @@
 "0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)"
 "0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)"
 "0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)"
-"0x5657","RV370_5657","RV380",,,,,,"ATI Radeon X550XTX (RV370) 5657 (PCIE)"
 "0x5B64","RV370_5B64","RV380",,,,,,"ATI FireGL V3100 (RV370) 5B64 (PCIE)"
 "0x5B65","RV370_5B65","RV380",,,,,,"ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)"
 "0x5C61","RV280_5C61","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)"
diff --git a/src/radeon.h b/src/radeon.h
index 94611a8a..4f77c3b9 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -220,7 +220,7 @@ typedef struct {
 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
 #define RADEON_PLL_USE_REF_DIV     (1 << 2)
 #define RADEON_PLL_LEGACY          (1 << 3)
-#define RADEON_PLL_DCE3            (1 << 4)
+#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
 
 typedef struct {
     uint16_t          reference_freq;
@@ -880,6 +880,7 @@ extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn);
 extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn);
 
 /* radeon_crtc.c */
+extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode);
 extern void radeon_crtc_load_lut(xf86CrtcPtr crtc);
 extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post);
 extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 5897c7e6..d45e932b 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -381,7 +381,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
 
 	if (drmCommandWriteRead(info->drmFD, DRM_RADEON_GETPARAM, &np,
 				sizeof(np)) < 0) {
-	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+	    xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
 		       "Failed to determine num pipes from DRM, falling back to "
 		       "manual look-up!\n");
 	    info->num_gb_pipes = 0;
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index e24697b9..900e9289 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1787,13 +1787,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
 	    continue;
 	}
 #endif
-#if 1
-	if (i == ATOM_DEVICE_TV1_INDEX) {
-	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping TV-Out\n");
-	    info->BiosConnector[i].valid = FALSE;
-	    continue;
-	}
-#endif
 
 	info->BiosConnector[i].valid = TRUE;
 	info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux;
@@ -2054,8 +2047,8 @@ UINT32
 CailReadATIRegister(VOID* CAIL, UINT32 idx)
 {
     ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
-    RADEONInfoPtr  info   = RADEONPTR(pScrn);
-    unsigned char *RADEONMMIO = info->MMIO;
+    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+    unsigned char *RADEONMMIO = pRADEONEnt->MMIO;
     UINT32 ret;
     CAILFUNC(CAIL);
 
@@ -2068,8 +2061,8 @@ VOID
 CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data)
 {
     ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex];
-    RADEONInfoPtr  info   = RADEONPTR(pScrn);
-    unsigned char *RADEONMMIO = info->MMIO;
+    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+    unsigned char *RADEONMMIO = pRADEONEnt->MMIO;
     CAILFUNC(CAIL);
 
     OUTREG(idx << 2,data);
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index fbcebae3..ed3174a0 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -96,6 +96,7 @@ RADEONCardInfo RADEONCards[] = {
  { 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
  { 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
  { 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
+ { 0x5657, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
  { 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 },
  { 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 },
  { 0x5954, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 },
@@ -115,7 +116,6 @@ RADEONCardInfo RADEONCards[] = {
  { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
  { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
  { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
- { 0x5657, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
  { 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
  { 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
  { 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 },
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index b60e7e8f..d1761d28 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -96,6 +96,7 @@ static SymTabRec RADEONChipsets[] = {
   { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" },
   { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" },
   { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" },
+  { PCI_CHIP_RV410_5657, "ATI Radeon X550XTX 5657 (PCIE)" },
   { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" },
   { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" },
   { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" },
@@ -115,7 +116,6 @@ static SymTabRec RADEONChipsets[] = {
   { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" },
   { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" },
   { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" },
-  { PCI_CHIP_RV370_5657, "ATI Radeon X550XTX (RV370) 5657 (PCIE)" },
   { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" },
   { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" },
   { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" },
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index b1e978c0..c63b6505 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -59,7 +59,7 @@ extern void atombios_crtc_mode_set(xf86CrtcPtr crtc,
 				   int x, int y);
 extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode);
 
-static void
+void
 radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
 {
     RADEONInfoPtr info = RADEONPTR(crtc->scrn);
@@ -110,7 +110,6 @@ radeon_crtc_mode_prepare(xf86CrtcPtr crtc)
 
     if (radeon_crtc->enabled)
 	crtc->funcs->hide_cursor(crtc);
-    radeon_crtc_dpms(crtc, DPMSModeOff);
 }
 
 static uint32_t RADEONDiv(CARD64 n, uint32_t d)
@@ -133,7 +132,7 @@ RADEONComputePLL(RADEONPLLPtr pll,
     uint32_t best_post_div = 1;
     uint32_t best_ref_div = 1;
     uint32_t best_feedback_div = 1;
-    uint32_t best_freq = 1;
+    uint32_t best_freq = -1;
     uint32_t best_error = 0xffffffff;
     uint32_t best_vco_diff = 1;
     uint32_t post_div;
@@ -144,10 +143,20 @@ RADEONComputePLL(RADEONPLLPtr pll,
 
     if (flags & RADEON_PLL_USE_REF_DIV)
 	min_ref_div = max_ref_div = pll->reference_div;
+    else {
+	while (min_ref_div < max_ref_div-1) {
+	    uint32_t mid=(min_ref_div+max_ref_div)/2;
+	    uint32_t pll_in = pll->reference_freq / mid;
+	    if (pll_in < pll->pll_in_min)
+		max_ref_div = mid;
+	    else if (pll_in > pll->pll_in_max)
+		min_ref_div = mid;
+	    else break;
+	}
+    }
 
     for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
 	uint32_t ref_div;
-	uint32_t vco = (freq / 10000) * post_div;
 
 	if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 	    continue;
@@ -162,45 +171,71 @@ RADEONComputePLL(RADEONPLLPtr pll,
 		continue;
 	}
 
-	if (vco < pll->pll_out_min || vco > pll->pll_out_max)
-	    continue;
-
 	for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 	    uint32_t feedback_div, current_freq, error, vco_diff;
 	    uint32_t pll_in = pll->reference_freq / ref_div;
+	    uint32_t min_feed_div = pll->min_feedback_div;
+	    uint32_t max_feed_div = pll->max_feedback_div+1;
 
 	    if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 		continue;
 
-	    feedback_div = RADEONDiv((CARD64)freq * ref_div * post_div,
-				     pll->reference_freq * 10000);
+	    while (min_feed_div < max_feed_div) {
+		uint32_t vco;
 
-	    if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div)
-		continue;
+		feedback_div = (min_feed_div+max_feed_div)/2;
+
+		vco = RADEONDiv((CARD64)pll->reference_freq * feedback_div,
+				ref_div);
+
+		if (vco < pll->pll_out_min) {
+		    min_feed_div = feedback_div+1;
+		    continue;
+		} else if(vco > pll->pll_out_max) {
+		    max_feed_div = feedback_div;
+		    continue;
+		}
+
+		current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div,
+					 ref_div * post_div);
+
+		error = abs(current_freq - freq);
+		vco_diff = abs(vco - best_vco);
+
+		if ((best_vco == 0 && error < best_error) ||
+		    (best_vco != 0 &&
+		     (error < best_error - 100 ||
+		      (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) {
+		    best_post_div = post_div;
+		    best_ref_div = ref_div;
+		    best_feedback_div = feedback_div;
+		    best_freq = current_freq;
+		    best_error = error;
+		    best_vco_diff = vco_diff;
+		} else if (current_freq == freq) {
+		    if (best_freq == -1) {
+			best_post_div = post_div;
+			best_ref_div = ref_div;
+			best_feedback_div = feedback_div;
+			best_freq = current_freq;
+			best_error = error;
+			best_vco_diff = vco_diff;
+		    } else if ((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) {
+			best_post_div = post_div;
+			best_ref_div = ref_div;
+			best_feedback_div = feedback_div;
+			best_freq = current_freq;
+			best_error = error;
+			best_vco_diff = vco_diff;
+		    }
+		}
 
-	    current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div,
-				     ref_div * post_div);
-
-	    error = abs(current_freq - freq);
-	    vco_diff = abs(vco - best_vco);
-
-	    if ((best_vco == 0 && error < best_error) ||
-		(ref_div == pll->reference_div) ||
-		(best_vco != 0 &&
-		 (error < best_error - 100 ||
-		  (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) {
-		best_post_div = post_div;
-		best_ref_div = ref_div;
-		best_feedback_div = feedback_div;
-		best_freq = current_freq;
-		best_error = error;
-		best_vco_diff = vco_diff;
+		if (current_freq < freq)
+		    min_feed_div = feedback_div+1;
+		else
+		    max_feed_div = feedback_div;
 	    }
 	}
-	if (!(flags & RADEON_PLL_DCE3)) {
-	    if (best_freq == freq)
-		break;
-	}
     }
 
     ErrorF("best_freq: %u\n", (unsigned int)best_freq);
@@ -208,6 +243,8 @@ RADEONComputePLL(RADEONPLLPtr pll,
     ErrorF("best_ref_div: %u\n", (unsigned int)best_ref_div);
     ErrorF("best_post_div: %u\n", (unsigned int)best_post_div);
 
+    if (best_freq == -1)
+	FatalError("Couldn't find valid PLL dividers\n");
     *chosen_dot_clock_freq = best_freq / 10000;
     *chosen_feedback_div = best_feedback_div;
     *chosen_reference_div = best_ref_div;
@@ -232,25 +269,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 static void
 radeon_crtc_mode_commit(xf86CrtcPtr crtc)
 {
-    RADEONInfoPtr info = RADEONPTR(crtc->scrn);
-    RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
-    RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
-    if (info->ChipFamily >= CHIP_FAMILY_R600) {
-	xf86CrtcPtr other;
-	if (radeon_crtc->crtc_id == 1)
-	    other = pRADEONEnt->pCrtc[0];
-	else
-	    other = pRADEONEnt->pCrtc[1];
-	if (other->enabled)
-	    radeon_crtc_dpms(other, DPMSModeOn);
-    }
-
-    radeon_crtc_dpms(crtc, DPMSModeOn);
-
     if (crtc->scrn->pScreen != NULL)
 	xf86_reload_cursors(crtc->scrn->pScreen);
-
 }
 
 void
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 25165905..f18ad993 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -224,8 +224,7 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
     stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
     *size = stride;
 
-    return ((uint8_t *)info->FB + pScrn->fbOffset +
-            row * stride + offset);
+    return ((uint8_t *)info->FB + row * stride + offset);
 }
 static Bool
 RADEONCreateScreenResources (ScreenPtr pScreen)
diff --git a/src/radeon_macros.h b/src/radeon_macros.h
index 3675dc51..afe442ea 100644
--- a/src/radeon_macros.h
+++ b/src/radeon_macros.h
@@ -51,7 +51,23 @@
 
 #include "compiler.h"
 
+#if HAVE_BYTESWAP_H
 #include <byteswap.h>
+#elif defined(USE_SYS_ENDIAN_H)
+#include <sys/endian.h>
+#else
+#define	bswap_16(value)  \
+ 	((((value) & 0xff) << 8) | ((value) >> 8))
+
+#define	bswap_32(value)	\
+ 	(((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \
+ 	(uint32_t)bswap_16((uint16_t)((value) >> 16)))
+ 
+#define	bswap_64(value)	\
+ 	(((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \
+ 	    << 32) | \
+ 	(uint64_t)bswap_32((uint32_t)((value) >> 32)))
+#endif
 
 #if X_BYTE_ORDER == X_BIG_ENDIAN
 #define le32_to_cpu(x) bswap_32(x)
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 72addefb..7b89d66e 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -74,12 +74,13 @@ const RADEONMonitorType MonTypeID[10] = {
   MT_DP
 };
 
-const char *TMDSTypeName[5] = {
+const char *TMDSTypeName[6] = {
   "None",
   "Internal",
   "External",
   "LVTMA",
-  "DDIA"
+  "DDIA",
+  "UNIPHY"
 };
 
 const char *DACTypeName[4] = {
@@ -143,6 +144,7 @@ static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] =
     {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},		/*CHIP_FAMILY_R420*/
     {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},		/*CHIP_FAMILY_RV410*/ /* FIXME: just values from r420 used... */
     {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},	/*CHIP_FAMILY_RS400*/ /* FIXME: just values from rv380 used... */
+    {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},	/*CHIP_FAMILY_RS480*/ /* FIXME: just values from rv380 used... */
 };
 
 static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] =
@@ -165,6 +167,7 @@ static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] =
     0x01080000,   /* r420 */
     0x01080000,   /* rv410 */ /* FIXME: just values from r420 used... */
     0x00780000,   /* rs400 */ /* FIXME: just values from rv380 used... */
+    0x00780000,   /* rs480 */ /* FIXME: just values from rv380 used... */
 };
 
 
@@ -583,8 +586,26 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
 static void
 radeon_mode_prepare(xf86OutputPtr output)
 {
+    xf86CrtcConfigPtr	config = XF86_CRTC_CONFIG_PTR (output->scrn);
+    int o;
+
+    for (o = 0; o < config->num_output; o++) {
+	xf86OutputPtr loop_output = config->output[o];
+	if (loop_output == output)
+	    continue;
+	else if (loop_output->crtc) {
+	    xf86CrtcPtr other_crtc = loop_output->crtc;
+	    if (other_crtc->enabled) {
+		radeon_dpms(loop_output, DPMSModeOff);
+		radeon_crtc_dpms(other_crtc, DPMSModeOff);
+	    }
+	}
+    }
+
     radeon_bios_output_lock(output, TRUE);
     radeon_dpms(output, DPMSModeOff);
+    radeon_crtc_dpms(output->crtc, DPMSModeOff);
+
 }
 
 static void
@@ -604,7 +625,24 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
 static void
 radeon_mode_commit(xf86OutputPtr output)
 {
+    xf86CrtcConfigPtr	config = XF86_CRTC_CONFIG_PTR (output->scrn);
+    int o;
+
+    for (o = 0; o < config->num_output; o++) {
+	xf86OutputPtr loop_output = config->output[o];
+	if (loop_output == output)
+	    continue;
+	else if (loop_output->crtc) {
+	    xf86CrtcPtr other_crtc = loop_output->crtc;
+	    if (other_crtc->enabled) {
+		radeon_dpms(loop_output, DPMSModeOn);		
+		radeon_crtc_dpms(other_crtc, DPMSModeOn);
+	    }
+	}
+    }
+
     radeon_dpms(output, DPMSModeOn);
+    radeon_crtc_dpms(output->crtc, DPMSModeOn);
     radeon_bios_output_lock(output, FALSE);
 }
 
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 7e4cb172..39adb5e3 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -96,6 +96,7 @@ PciChipsets RADEONPciChipsets[] = {
  { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA },
  { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA },
  { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_5657, PCI_CHIP_RV410_5657, RES_SHARED_VGA },
  { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA },
  { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA },
  { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA },
@@ -115,7 +116,6 @@ PciChipsets RADEONPciChipsets[] = {
  { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA },
  { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA },
  { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5657, PCI_CHIP_RV370_5657, RES_SHARED_VGA },
  { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA },
  { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA },
  { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA },
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 72ff0d17..d81cbe37 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -96,6 +96,7 @@ static const struct pci_id_match radeon_device_match[] = {
  ATI_DEVICE_MATCH( PCI_CHIP_RV410_564F, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_RV410_5652, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_RV410_5653, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV410_5657, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_RS300_5834, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_RS300_5835, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_RS480_5954, 0 ),
@@ -115,7 +116,6 @@ static const struct pci_id_match radeon_device_match[] = {
  ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B60, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B62, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B63, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5657, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B64, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B65, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C61, 0 ),