R3xx+: more fixes to 2D/3D engine init

3 files changed, 73 insertions, 39 deletions

diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 7865de1b..9fecce6e 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -370,7 +370,52 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
 		   info->CurrentLayout.pixel_code,
 		   info->CurrentLayout.bitsPerPixel);
 
-    OUTREG(RADEON_RB3D_CNTL, 0);
+    if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
+	(info->ChipFamily == CHIP_FAMILY_R420)  ||
+	(info->ChipFamily == CHIP_FAMILY_RS690) ||
+	(info->ChipFamily == CHIP_FAMILY_RS740) ||
+	(info->ChipFamily == CHIP_FAMILY_RS400) ||
+	IS_R500_3D) {
+	uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
+	if (info->num_gb_pipes == 0) {
+	    info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
+	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+		       "%s: num pipes is %d\n", __FUNCTION__, info->num_gb_pipes);
+	}
+	if (IS_R500_3D)
+	    OUTPLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
+    } else {
+	if (info->num_gb_pipes == 0) {
+	    if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+		(info->ChipFamily == CHIP_FAMILY_R350)) {
+		/* R3xx chips */
+		info->num_gb_pipes = 2;
+	    } else {
+		/* RV3xx chips */
+		info->num_gb_pipes = 1;
+	    }
+	}
+    }
+
+    if (IS_R300_3D | IS_R500_3D) {
+	CARD32 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
+
+	switch(info->num_gb_pipes) {
+	case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
+	case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
+	case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
+	default:
+	case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
+	}
+
+	OUTREG(R300_GB_TILE_CONFIG, gb_tile_config);
+	OUTREG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN);
+	OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
+	OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) |
+					 R300_DC_AUTOFLUSH_ENABLE |
+					 R300_DC_DC_DISABLE_IGNORE_PE));
+    } else
+	OUTREG(RADEON_RB3D_CNTL, 0);
 
     RADEONEngineReset(pScrn);
 
@@ -415,33 +460,6 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
     info->aux_sc_cntl     = 0x00000000;
 #endif
 
-    if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
-	(info->ChipFamily == CHIP_FAMILY_R420)  ||
-	(info->ChipFamily == CHIP_FAMILY_RS690) ||
-	(info->ChipFamily == CHIP_FAMILY_RS740) ||
-	(info->ChipFamily == CHIP_FAMILY_RS400) ||
-	IS_R500_3D) {
-	uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
-	if (info->num_gb_pipes == 0) {
-	    info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
-	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-		       "%s: num pipes is %d\n", __FUNCTION__, info->num_gb_pipes);
-	}
-	if (IS_R500_3D)
-	    OUTPLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
-    } else {
-	if (info->num_gb_pipes == 0) {
-	    if ((info->ChipFamily == CHIP_FAMILY_R300) ||
-		(info->ChipFamily == CHIP_FAMILY_R350)) {
-		/* R3xx chips */
-		info->num_gb_pipes = 2;
-	    } else {
-		/* RV3xx chips */
-		info->num_gb_pipes = 1;
-	    }
-	}
-    }
-
     RADEONEngineRestore(pScrn);
 }
 
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 025fb564..ec4b434c 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -80,8 +80,10 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 	}
 
-	BEGIN_ACCEL(3);
+	BEGIN_ACCEL(5);
 	OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config);
+	OUT_ACCEL_REG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN);
+	OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
 	OUT_ACCEL_REG(R300_GB_SELECT, 0);
 	OUT_ACCEL_REG(R300_GB_ENABLE, 0);
 	FINISH_ACCEL();
@@ -121,7 +123,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 				       (8 << R300_MSBD1_SHIFT)));
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(4);
+	BEGIN_ACCEL(5);
+	OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 	OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 	OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
 					   R300_COLOR_ROUND_NEAREST));
@@ -145,18 +148,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	FINISH_ACCEL();
 
 	/* setup the VAP */	
-	if (info->has_tcl) {
-	    BEGIN_ACCEL(11);
-	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
-	} else {
-	    BEGIN_ACCEL(5);
-	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
-	}
+	if (info->has_tcl)
+	    BEGIN_ACCEL(13);
+	else
+	    BEGIN_ACCEL(7);
+	OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0);
 	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
-	OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
+	OUT_ACCEL_REG(R300_VAP_CNTL, ((5/*6*/ << R300_PVS_NUM_SLOTS_SHIFT) |
 				      (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 				      (4 << R300_PVS_NUM_FPUS_SHIFT) |
-				      (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
+				      (9/*12*/ << R300_VF_MAX_VTX_NUM_SHIFT)));
+	if (info->has_tcl)
+	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
+	else
+	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
+	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 	OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
 	OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
 
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index aaac052c..51128721 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3904,6 +3904,10 @@
 #       define R300_MS_Y5_SHIFT                         20
 #       define R300_MSBD1_SHIFT                         24
 
+#define R300_GA_ENHANCE				        0x4274
+#       define R300_GA_DEADLOCK_CNTL                    (1 << 0)
+#       define R300_GA_FASTSYNC_CNTL                    (1 << 1)
+
 #define R300_GA_POLY_MODE				0x4288
 #       define R300_FRONT_PTYPE_POINT                   (0 << 4)
 #       define R300_FRONT_PTYPE_LINE                    (1 << 4)
@@ -3966,6 +3970,7 @@
 #       define R300_VTX_XY_FMT                          (1 << 8)
 #       define R300_VTX_Z_FMT                           (1 << 9)
 #       define R300_VTX_W0_FMT                          (1 << 10)
+#define R300_VAP_VTX_STATE_CNTL		                0x2180
 #define R300_VAP_PSC_SGN_NORM_CNTL		        0x21DC
 #define R300_VAP_PROG_STREAM_CNTL_0		        0x2150
 #       define R300_DATA_TYPE_0_SHIFT                   0
@@ -4610,6 +4615,11 @@
 #define R300_FG_FOG_BLEND				0x4bc0
 #define R300_FG_ALPHA_FUNC				0x4bd4
 
+#define R300_DST_PIPE_CONFIG		                0x170c
+#       define R300_PIPE_AUTO_CONFIG                    (1 << 31)
+#define R300_RB2D_DSTCACHE_MODE		                0x3428
+#       define R300_DC_AUTOFLUSH_ENABLE                 (1 << 8)
+#       define R300_DC_DC_DISABLE_IGNORE_PE             (1 << 17)
 #define R300_RB2D_DSTCACHE_CTLSTAT		        0x342c
 #       define R300_DC_FLUSH_2D                         (1 << 0)
 #       define R300_DC_FREE_2D                          (1 << 2)