diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2009-04-16 12:52:41 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2009-04-16 12:52:41 -0400 |
| commit | 2b95de17781959457a809c8fecc6bbb08336c83f (patch) | |
| tree | 71b2142cf7a671a875ff19f823b6a2870f0b3b4b | |
| parent | c0215d2f2a27755fb04d20aaa4320a5e7da7ee04 (diff) | |
RS400/RS480: attempt to fix ClockGating on RS4xx chips
| -rw-r--r-- | src/radeon_pm.c | 81 |
1 files changed, 80 insertions, 1 deletions
diff --git a/src/radeon_pm.c b/src/radeon_pm.c index 778919eb..8147786b 100644 --- a/src/radeon_pm.c +++ b/src/radeon_pm.c @@ -121,7 +121,47 @@ static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable) RADEON_SCLK_FORCE_TDM); OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); } else if (IS_R300_VARIANT) { - if (info->ChipFamily >= CHIP_FAMILY_RV350) { + if ((info->ChipFamily == CHIP_FAMILY_RS400) || + (info->ChipFamily == CHIP_FAMILY_RS480)) { + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | + RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | + RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | + R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | + RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | + R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | + R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | + R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); + tmp |= RADEON_DYN_STOP_LAT_MASK; + tmp |= RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_VIP; + OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); + tmp &= ~RADEON_SCLK_MORE_FORCEON; + tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; + OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); + tmp |= (RADEON_PIXCLK_ALWAYS_ONb | + RADEON_PIXCLK_DAC_ALWAYS_ONb); + OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); + tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | + RADEON_PIX2CLK_DAC_ALWAYS_ONb | + RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | + R300_DVOCLK_ALWAYS_ONb | + RADEON_PIXCLK_BLEND_ALWAYS_ONb | + RADEON_PIXCLK_GV_ALWAYS_ONb | + R300_PIXCLK_DVO_ALWAYS_ONb | + RADEON_PIXCLK_LVDS_ALWAYS_ONb | + RADEON_PIXCLK_TMDS_ALWAYS_ONb | + R300_PIXCLK_TRANS_ALWAYS_ONb | + R300_PIXCLK_TVO_ALWAYS_ONb | + R300_P2G2CLK_ALWAYS_ONb | + R300_P2G2CLK_ALWAYS_ONb); + OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); + } else if (info->ChipFamily >= CHIP_FAMILY_RV350) { tmp = INPLL(pScrn, R300_SCLK_CNTL2); tmp &= ~(R300_SCLK_FORCE_TCL | R300_SCLK_FORCE_GA | @@ -312,6 +352,45 @@ static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable) RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM | RADEON_SCLK_FORCE_RB); OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); + } else if ((info->ChipFamily == CHIP_FAMILY_RS400) || + (info->ChipFamily == CHIP_FAMILY_RS480)) { + tmp = INPLL(pScrn, RADEON_SCLK_CNTL); + tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | + RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | + RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | + R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | + RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | + R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | + R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | + R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); + OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); + tmp |= RADEON_SCLK_MORE_FORCEON; + OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); + tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | + RADEON_PIXCLK_DAC_ALWAYS_ONb | + R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); + OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); + + tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); + tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | + RADEON_PIX2CLK_DAC_ALWAYS_ONb | + RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | + R300_DVOCLK_ALWAYS_ONb | + RADEON_PIXCLK_BLEND_ALWAYS_ONb | + RADEON_PIXCLK_GV_ALWAYS_ONb | + R300_PIXCLK_DVO_ALWAYS_ONb | + RADEON_PIXCLK_LVDS_ALWAYS_ONb | + RADEON_PIXCLK_TMDS_ALWAYS_ONb | + R300_PIXCLK_TRANS_ALWAYS_ONb | + R300_PIXCLK_TVO_ALWAYS_ONb | + R300_P2G2CLK_ALWAYS_ONb | + R300_P2G2CLK_ALWAYS_ONb | + R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); + OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); } else if (info->ChipFamily >= CHIP_FAMILY_RV350) { /* for RV350/M10, no delays are required. */ tmp = INPLL(pScrn, R300_SCLK_CNTL2); |