summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAlex Deucher <alexdeucher@gmail.com>2011-01-11 16:21:18 -0500
committerAlex Deucher <alexdeucher@gmail.com>2011-01-11 16:21:18 -0500
commitc5b3db18d888552328e9718ea022794fc5bde352 (patch)
tree1f6d1f95b1037380664b226317961c719e62d1d5
parentbbd7adce889359b5eb3239b73e904b3ede283e12 (diff)
kms: fix pitch aligment for scanout
Display has slightly stricter pitch alignment requirements than other blocks. Factor that in when aligning pitch. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=32997
-rw-r--r--src/drmmode_display.c17
1 files changed, 14 insertions, 3 deletions
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index b7d01c4e..2ab4510c 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1118,14 +1118,25 @@ int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling)
int pitch_align = 1;
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- if (tiling & RADEON_TILING_MACRO)
+ if (tiling & RADEON_TILING_MACRO) {
+ /* general surface requirements */
pitch_align = MAX(info->num_banks,
(((info->group_bytes / 8) / bpe) * info->num_banks)) * 8;
- else if (tiling & RADEON_TILING_MICRO)
+ /* further restrictions for scanout */
+ pitch_align = MAX(info->num_banks * 8, pitch_align);
+ } else if (tiling & RADEON_TILING_MICRO) {
+ /* general surface requirements */
pitch_align = MAX(8, (info->group_bytes / (8 * bpe)));
- else
+ /* further restrictions for scanout */
+ pitch_align = MAX(info->group_bytes / bpe, pitch_align);
+ } else {
+ /* general surface requirements */
pitch_align = info->group_bytes / bpe;
+ /* further restrictions for scanout */
+ pitch_align = MAX(32, pitch_align);
+ }
} else {
+ /* general surface requirements */
if (tiling)
pitch_align = 256 / bpe;
else