diff options
author | Alex Deucher <alex@botch2.(none)> | 2007-11-03 18:20:55 -0400 |
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committer | Alex Deucher <alex@botch2.(none)> | 2007-11-03 18:20:55 -0400 |
commit | e18f5d61806b445ad77d93e258fbce9422b52bb6 (patch) | |
tree | 41f19d7299460d9606f523f8e3231d234f6c2996 | |
parent | 49cf7cb3db36ce7734f7e314a040a240191d6477 (diff) |
Initial integration of Atom code and some of Dave's code.
ATOM builds, but it's not hooked up yet.
-rw-r--r-- | src/AtomBios/CD_Operations.c | 954 | ||||
-rw-r--r-- | src/AtomBios/Decoder.c | 235 | ||||
-rw-r--r-- | src/AtomBios/hwserv_drv.c | 348 | ||||
-rw-r--r-- | src/AtomBios/includes/CD_Common_Types.h | 150 | ||||
-rw-r--r-- | src/AtomBios/includes/CD_Definitions.h | 49 | ||||
-rw-r--r-- | src/AtomBios/includes/CD_Opcodes.h | 181 | ||||
-rw-r--r-- | src/AtomBios/includes/CD_Structs.h | 464 | ||||
-rw-r--r-- | src/AtomBios/includes/CD_binding.h | 46 | ||||
-rw-r--r-- | src/AtomBios/includes/CD_hw_services.h | 318 | ||||
-rw-r--r-- | src/AtomBios/includes/Decoder.h | 86 | ||||
-rw-r--r-- | src/AtomBios/includes/atombios.h | 4306 | ||||
-rw-r--r-- | src/AtomBios/includes/regsdef.h | 25 | ||||
-rw-r--r-- | src/Makefile.am | 20 | ||||
-rw-r--r-- | src/avivo_reg.h | 503 | ||||
-rw-r--r-- | src/radeon.h | 11 | ||||
-rw-r--r-- | src/radeon_atombios.c | 1104 | ||||
-rw-r--r-- | src/radeon_atombios.h | 202 | ||||
-rw-r--r-- | src/radeon_atomwrapper.c | 97 | ||||
-rw-r--r-- | src/radeon_atomwrapper.h | 31 | ||||
-rw-r--r-- | src/radeon_probe.h | 13 |
20 files changed, 9141 insertions, 2 deletions
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c new file mode 100644 index 00000000..1e48f815 --- /dev/null +++ b/src/AtomBios/CD_Operations.c @@ -0,0 +1,954 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + +Module Name: + + CD_Operations.c + +Abstract: + + Functions Implementing Command Operations and other common functions + +Revision History: + + NEG:27.09.2002 Initiated. +--*/ +#define __SW_4 + +#include "Decoder.h" +#include "atombios.h" + + + +VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + +UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + +UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + +VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + +UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + +UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData); +UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable); + + +WRITE_IO_FUNCTION WritePCIFunctions[8] = { + WritePCIReg32, + WritePCIReg16, WritePCIReg16, WritePCIReg16, + WritePCIReg8,WritePCIReg8,WritePCIReg8,WritePCIReg8 +}; +WRITE_IO_FUNCTION WriteIOFunctions[8] = { + WriteSysIOReg32, + WriteSysIOReg16,WriteSysIOReg16,WriteSysIOReg16, + WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8 +}; +READ_IO_FUNCTION ReadPCIFunctions[8] = { + (READ_IO_FUNCTION)ReadPCIReg32, + (READ_IO_FUNCTION)ReadPCIReg16, + (READ_IO_FUNCTION)ReadPCIReg16, + (READ_IO_FUNCTION)ReadPCIReg16, + (READ_IO_FUNCTION)ReadPCIReg8, + (READ_IO_FUNCTION)ReadPCIReg8, + (READ_IO_FUNCTION)ReadPCIReg8, + (READ_IO_FUNCTION)ReadPCIReg8 +}; +READ_IO_FUNCTION ReadIOFunctions[8] = { + (READ_IO_FUNCTION)ReadSysIOReg32, + (READ_IO_FUNCTION)ReadSysIOReg16, + (READ_IO_FUNCTION)ReadSysIOReg16, + (READ_IO_FUNCTION)ReadSysIOReg16, + (READ_IO_FUNCTION)ReadSysIOReg8, + (READ_IO_FUNCTION)ReadSysIOReg8, + (READ_IO_FUNCTION)ReadSysIOReg8, + (READ_IO_FUNCTION)ReadSysIOReg8 +}; +READ_IO_FUNCTION GetParametersDirectArray[8]={ + GetParametersDirect32, + GetParametersDirect16,GetParametersDirect16,GetParametersDirect16, + GetParametersDirect8,GetParametersDirect8,GetParametersDirect8, + GetParametersDirect8 +}; + +COMMANDS_DECODER PutDataFunctions[6] = { + PutDataRegister, + PutDataPS, + PutDataWS, + PutDataFB, + PutDataPLL, + PutDataMC +}; +CD_GET_PARAMETERS GetDestination[6] = { + GetParametersRegister, + GetParametersPS, + GetParametersWS, + GetParametersFB, + GetParametersPLL, + GetParametersMC +}; + +COMMANDS_DECODER SkipDestination[6] = { + SkipParameters16, + SkipParameters8, + SkipParameters8, + SkipParameters8, + SkipParameters8, + SkipParameters8 +}; + +CD_GET_PARAMETERS GetSource[8] = { + GetParametersRegister, + GetParametersPS, + GetParametersWS, + GetParametersFB, + GetParametersIndirect, + GetParametersDirect, + GetParametersPLL, + GetParametersMC +}; + +UINT32 AlignmentMask[8] = {0xFFFFFFFF,0xFFFF,0xFFFF,0xFFFF,0xFF,0xFF,0xFF,0xFF}; +UINT8 SourceAlignmentShift[8] = {0,0,8,16,0,8,16,24}; +UINT8 DestinationAlignmentShift[4] = {0,8,16,24}; + +#define INDIRECTIO_ID 1 +#define INDIRECTIO_END_OF_ID 9 + +VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +VOID IndirectIOCommand_MOVE(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT32 temp); +VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + +INDIRECT_IO_PARSER_COMMANDS IndirectIOParserCommands[10]={ + {IndirectIOCommand,1}, + {IndirectIOCommand,2}, + {ReadIndReg32,3}, + {WriteIndReg32,3}, + {IndirectIOCommand_CLEAR,3}, + {IndirectIOCommand_SET,3}, + {IndirectIOCommand_MOVE_INDEX,4}, + {IndirectIOCommand_MOVE_ATTR,4}, + {IndirectIOCommand_MOVE_DATA,4}, + {IndirectIOCommand,3} +}; + + +VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ +} + + +VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); + pParserTempData->IndirectData |=(((pParserTempData->Index >> pParserTempData->IndirectIOTablePointer[2]) & + (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); +} + +VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); + pParserTempData->IndirectData |=(((pParserTempData->AttributesData >> pParserTempData->IndirectIOTablePointer[2]) + & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); +} + +VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); + pParserTempData->IndirectData |=(((pParserTempData->DestData32 >> pParserTempData->IndirectIOTablePointer[2]) + & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); +} + + +VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->IndirectData |= ((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]); +} + +VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]); +} + + +UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + // if ((pParserTempData->IndirectData & 0x7f)==INDIRECT_IO_MM) pParserTempData->IndirectData|=pParserTempData->CurrentPortID; +// pParserTempData->IndirectIOTablePointer=pParserTempData->IndirectIOTable; + while (*pParserTempData->IndirectIOTablePointer) + { + if ((pParserTempData->IndirectIOTablePointer[0] == INDIRECTIO_ID) && + (pParserTempData->IndirectIOTablePointer[1] == pParserTempData->IndirectData)) + { + pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; + while (*pParserTempData->IndirectIOTablePointer != INDIRECTIO_END_OF_ID) + { + IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData); + pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; + } + pParserTempData->IndirectIOTablePointer-=*(UINT16*)(pParserTempData->IndirectIOTablePointer+1); + pParserTempData->IndirectIOTablePointer++; + return pParserTempData->IndirectData; + } else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; + } + return 0; +} + + + +VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.WordXX.PA_Destination; + pParserTempData->Index+=pParserTempData->CurrentRegBlock; + switch(pParserTempData->Multipurpose.CurrentPort){ + case ATI_RegsPort: + if (pParserTempData->CurrentPortID == INDIRECT_IO_MM) + { + if (pParserTempData->Index==0) pParserTempData->DestData32 <<= 2; + WriteReg32( pParserTempData); + } else + { + pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_WRITE; + IndirectInputOutput(pParserTempData); + } + break; + case PCI_Port: + WritePCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); + break; + case SystemIO_Port: + WriteIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); + break; + } +} + +VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)= + pParserTempData->DestData32; +} + +VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + if (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination < WS_QUOTIENT_C) + *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32; + else + switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) + { + case WS_REMINDER_C: + pParserTempData->MultiplicationOrDivision.Division.Reminder32=pParserTempData->DestData32; + break; + case WS_QUOTIENT_C: + pParserTempData->MultiplicationOrDivision.Division.Quotient32=pParserTempData->DestData32; + break; + case WS_DATAPTR_C: +#ifndef UEFI_BUILD + pParserTempData->CurrentDataBlock=(UINT16)pParserTempData->DestData32; +#else + pParserTempData->CurrentDataBlock=(UINTN)pParserTempData->DestData32; +#endif + break; + case WS_SHIFT_C: + pParserTempData->Shift2MaskConverter=(UINT8)pParserTempData->DestData32; + break; + case WS_FB_WINDOW_C: + pParserTempData->CurrentFB_Window=pParserTempData->DestData32; + break; + case WS_ATTRIBUTES_C: + pParserTempData->AttributesData=(UINT16)pParserTempData->DestData32; + break; + } + +} + +VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; + //Make an Index from address first, then add to the Index + pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2); + WriteFrameBuffer32(pParserTempData); +} + +VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; + WritePLL32( pParserTempData ); +} + +VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; + WriteMC32( pParserTempData ); +} + + +VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); +} + +VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); +} + + +UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; + pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); + pParserTempData->Index+=pParserTempData->CurrentRegBlock; + switch(pParserTempData->Multipurpose.CurrentPort) + { + case PCI_Port: + return ReadPCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); + case SystemIO_Port: + return ReadIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); + case ATI_RegsPort: + default: + if (pParserTempData->CurrentPortID == INDIRECT_IO_MM) return ReadReg32( pParserTempData ); + else + { + pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_READ; + return IndirectInputOutput(pParserTempData); + } + } +} + +UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; + pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); + return *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index); +} + +UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; + pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); + if (pParserTempData->Index < WS_QUOTIENT_C) + return *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->Index); + else + switch (pParserTempData->Index) + { + case WS_REMINDER_C: + return pParserTempData->MultiplicationOrDivision.Division.Reminder32; + case WS_QUOTIENT_C: + return pParserTempData->MultiplicationOrDivision.Division.Quotient32; + case WS_DATAPTR_C: + return (UINT32)pParserTempData->CurrentDataBlock; + case WS_OR_MASK_C: + return ((UINT32)1) << pParserTempData->Shift2MaskConverter; + case WS_AND_MASK_C: + return ~(((UINT32)1) << pParserTempData->Shift2MaskConverter); + case WS_FB_WINDOW_C: + return pParserTempData->CurrentFB_Window; + case WS_ATTRIBUTES_C: + return pParserTempData->AttributesData; + } + return 0; + +} + +UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; + pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); + pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2); + return ReadFrameBuffer32(pParserTempData); +} + +UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; + pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); + return ReadPLL32( pParserTempData ); +} + +UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; + pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); + return ReadMC32( pParserTempData ); +} + + +UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; + pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); + return *(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock); +} + +UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->CD_Mask.SrcAlignment=alignmentByte0; + pParserTempData->Index=*(UINT8*)pParserTempData->pWorkingTableData->IP; + pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); + return pParserTempData->Index; +} + +UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord; + pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; + pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); + return pParserTempData->Index; +} + +UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->CD_Mask.SrcAlignment=alignmentDword; + pParserTempData->Index=*(UINT32*)pParserTempData->pWorkingTableData->IP; + pParserTempData->pWorkingTableData->IP+=sizeof(UINT32); + return pParserTempData->Index; +} + + +UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + return GetParametersDirectArray[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); +} + + +VOID CommonSourceDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; + pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; + pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; +} + +VOID CommonOperationDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; + pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; + pParserTempData->DestData32 >>= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; + pParserTempData->DestData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; +} + +VOID ProcessMove(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword) + { + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + } else + { + SkipDestination[pParserTempData->ParametersType.Destination](pParserTempData); + } + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + + if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword) + { + pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); + CommonSourceDataTransformation(pParserTempData); + pParserTempData->DestData32 |= pParserTempData->SourceData32; + } else + { + pParserTempData->DestData32=pParserTempData->SourceData32; + } + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); +} + +VOID ProcessMask(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetParametersDirect(pParserTempData); + pParserTempData->Index=GetParametersDirect(pParserTempData); + pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; + pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); + pParserTempData->DestData32 &= pParserTempData->SourceData32; + pParserTempData->Index &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; + pParserTempData->Index <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; + pParserTempData->DestData32 |= pParserTempData->Index; + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); +} + +VOID ProcessAnd(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; + pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; + pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); + pParserTempData->DestData32 &= pParserTempData->SourceData32; + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); +} + +VOID ProcessOr(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + CommonSourceDataTransformation(pParserTempData); + pParserTempData->DestData32 |= pParserTempData->SourceData32; + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); +} + +VOID ProcessXor(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + CommonSourceDataTransformation(pParserTempData); + pParserTempData->DestData32 ^= pParserTempData->SourceData32; + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); +} + +VOID ProcessShl(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + CommonSourceDataTransformation(pParserTempData); + pParserTempData->DestData32 <<= pParserTempData->SourceData32; + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); +} + +VOID ProcessShr(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + CommonSourceDataTransformation(pParserTempData); + pParserTempData->DestData32 >>= pParserTempData->SourceData32; + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); +} + + +VOID ProcessADD(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + CommonSourceDataTransformation(pParserTempData); + pParserTempData->DestData32 += pParserTempData->SourceData32; + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); +} + +VOID ProcessSUB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + CommonSourceDataTransformation(pParserTempData); + pParserTempData->DestData32 -= pParserTempData->SourceData32; + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); +} + +VOID ProcessMUL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + CommonOperationDataTransformation(pParserTempData); + pParserTempData->MultiplicationOrDivision.Multiplication.Low32Bit=pParserTempData->DestData32 * pParserTempData->SourceData32; +} + +VOID ProcessDIV(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + + CommonOperationDataTransformation(pParserTempData); + pParserTempData->MultiplicationOrDivision.Division.Quotient32= + pParserTempData->DestData32 / pParserTempData->SourceData32; + pParserTempData->MultiplicationOrDivision.Division.Reminder32= + pParserTempData->DestData32 % pParserTempData->SourceData32; +} + + +VOID ProcessCompare(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + + CommonOperationDataTransformation(pParserTempData); + + // Here we just set flags based on evaluation + if (pParserTempData->DestData32==pParserTempData->SourceData32) + pParserTempData->CompareFlags = Equal; + else + pParserTempData->CompareFlags = + (UINT8)((pParserTempData->DestData32<pParserTempData->SourceData32) ? Below : Above); + +} + +VOID ProcessClear(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]); + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); + +} + +VOID ProcessShift(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + UINT32 mask = AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetParametersDirect8(pParserTempData); + + // save original value of the destination + pParserTempData->Index = pParserTempData->DestData32 & ~mask; + pParserTempData->DestData32 &= mask; + + if (pParserTempData->pCmd->Header.Opcode < SHIFT_RIGHT_REG_OPCODE) + pParserTempData->DestData32 <<= pParserTempData->SourceData32; else + pParserTempData->DestData32 >>= pParserTempData->SourceData32; + + // Clear any bits shifted out of masked area... + pParserTempData->DestData32 &= mask; + // ... and restore the area outside of masked with original values + pParserTempData->DestData32 |= pParserTempData->Index; + + // write data back + PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); +} + +VOID ProcessTest(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + CommonOperationDataTransformation(pParserTempData); + pParserTempData->CompareFlags = + (UINT8)((pParserTempData->DestData32 & pParserTempData->SourceData32) ? NotEqual : Equal); + +} + +VOID ProcessSetFB_Base(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; + pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; + pParserTempData->CurrentFB_Window=pParserTempData->SourceData32; +} + +VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; + pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; + while ( *(UINT16*)pParserTempData->pWorkingTableData->IP != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE)) + { + if (*pParserTempData->pWorkingTableData->IP == 'c') + { + pParserTempData->pWorkingTableData->IP++; + pParserTempData->DestData32=GetParametersDirect(pParserTempData); + pParserTempData->Index=GetParametersDirect16(pParserTempData); + if (pParserTempData->SourceData32 == pParserTempData->DestData32) + { + pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index); + return; + } + } + } + pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); +} + + +VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + UINT8 value; + UINT16* pMasterDataTable; + value=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; + if (value == 0) pParserTempData->CurrentDataBlock=0; else + { + if (value == DB_CURRENT_COMMAND_TABLE) + { + pParserTempData->CurrentDataBlock= (UINT16)(pParserTempData->pWorkingTableData->pTableHead-pParserTempData->pDeviceData->pBIOS_Image); + } else + { + pMasterDataTable = GetDataMasterTablePointer(pParserTempData->pDeviceData); + pParserTempData->CurrentDataBlock= (TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value]; + } + } + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); +} + +VOID cmdSet_ATI_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Multipurpose.CurrentPort=ATI_RegsPort; + pParserTempData->CurrentPortID = (UINT8)((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination; + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); +} + +VOID cmdSet_Reg_Block(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->CurrentRegBlock = ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination; + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); +} + + +//Atavism!!! Review!!! +VOID cmdSet_X_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ + pParserTempData->Multipurpose.CurrentPort=pParserTempData->ParametersType.Destination; + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_ONLY); + +} + +VOID cmdDelay_Millisec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ + pParserTempData->SourceData32 = + ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; + DelayMilliseconds(pParserTempData); + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); +} +VOID cmdDelay_Microsec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ + pParserTempData->SourceData32 = + ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; + DelayMicroseconds(pParserTempData); + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); +} + +VOID ProcessPostChar(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->SourceData32 = + ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; + PostCharOutput(pParserTempData); + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); +} + +VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->SourceData32 = + ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; + CallerDebugFunc(pParserTempData); + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); +} + + +VOID ProcessDS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->pWorkingTableData->IP+=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination+sizeof(COMMAND_TYPE_OPCODE_OFFSET16); +} + + +VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ + UINT16* MasterTableOffset; + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); + MasterTableOffset = GetCommandMasterTablePointer(pParserTempData->pDeviceData); + if(((PTABLE_UNIT_TYPE)MasterTableOffset)[((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value]!=0 ) // if the offset is not ZERO + { + pParserTempData->CommandSpecific.IndexInMasterTable=GetTrueIndexInMasterTable(pParserTempData,((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value); + pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable = + (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pParserTempData->pWorkingTableData->pTableHead)->TableAttribute.PS_SizeInBytes>>2); + pParserTempData->pDeviceData->pParameterSpace+= + pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable; + pParserTempData->Status=CD_CALL_TABLE; + pParserTempData->pCmd=(GENERIC_ATTRIBUTE_COMMAND*)MasterTableOffset; + } +} + + +VOID cmdNOP_(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ +} + + +static VOID NotImplemented(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + pParserTempData->Status = CD_NOT_IMPLEMENTED; +} + + +VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + if ((pParserTempData->ParametersType.Destination == NoCondition) || + (pParserTempData->ParametersType.Destination == pParserTempData->CompareFlags )) + { + + pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); + } else + { + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); + } +} + +VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + if ((pParserTempData->CompareFlags == Equal) || + (pParserTempData->CompareFlags == pParserTempData->ParametersType.Destination)) + { + + pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); + } else + { + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); + } +} + +VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + if (pParserTempData->CompareFlags != Equal) + { + + pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); + } else + { + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); + } +} + + + +COMMANDS_PROPERTIES CallTable[] = +{ + { NULL, 0,0}, + { ProcessMove, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessMove, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessMove, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessMove, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessMove, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessMove, destMC, sizeof(COMMAND_HEADER)}, + { ProcessAnd, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessAnd, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessAnd, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessAnd, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessAnd, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessAnd, destMC, sizeof(COMMAND_HEADER)}, + { ProcessOr, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessOr, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessOr, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessOr, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessOr, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessOr, destMC, sizeof(COMMAND_HEADER)}, + { ProcessShift, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessShift, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessShift, destMC, sizeof(COMMAND_HEADER)}, + { ProcessShift, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessShift, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessShift, destMC, sizeof(COMMAND_HEADER)}, + { ProcessMUL, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessMUL, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessMUL, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessMUL, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessMUL, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessMUL, destMC, sizeof(COMMAND_HEADER)}, + { ProcessDIV, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessDIV, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessDIV, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessDIV, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessDIV, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessDIV, destMC, sizeof(COMMAND_HEADER)}, + { ProcessADD, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessADD, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessADD, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessADD, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessADD, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessADD, destMC, sizeof(COMMAND_HEADER)}, + { ProcessSUB, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessSUB, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessSUB, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessSUB, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessSUB, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessSUB, destMC, sizeof(COMMAND_HEADER)}, + { cmdSet_ATI_Port, ATI_RegsPort, 0}, + { cmdSet_X_Port, PCI_Port, 0}, + { cmdSet_X_Port, SystemIO_Port, 0}, + { cmdSet_Reg_Block, 0, 0}, + { ProcessSetFB_Base,0, sizeof(COMMAND_HEADER)}, + { ProcessCompare, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessCompare, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessCompare, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessCompare, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessCompare, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessCompare, destMC, sizeof(COMMAND_HEADER)}, + { ProcessSwitch, 0, sizeof(COMMAND_HEADER)}, + { ProcessJump, NoCondition, 0}, + { ProcessJump, Equal, 0}, + { ProcessJump, Below, 0}, + { ProcessJump, Above, 0}, + { ProcessJumpE, Below, 0}, + { ProcessJumpE, Above, 0}, + { ProcessJumpNE, 0, 0}, + { ProcessTest, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessTest, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessTest, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessTest, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessTest, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessTest, destMC, sizeof(COMMAND_HEADER)}, + { cmdDelay_Millisec,0, 0}, + { cmdDelay_Microsec,0, 0}, + { cmdCall_Table, 0, 0}, + /*cmdRepeat*/ { NotImplemented, 0, 0}, + { ProcessClear, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessClear, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessClear, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessClear, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessClear, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessClear, destMC, sizeof(COMMAND_HEADER)}, + { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)}, + /*cmdEOT*/ { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)}, + { ProcessMask, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessMask, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessMask, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessMask, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessMask, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessMask, destMC, sizeof(COMMAND_HEADER)}, + /*cmdPost_Card*/ { ProcessPostChar, 0, 0}, + /*cmdBeep*/ { NotImplemented, 0, 0}, + /*cmdSave_Reg*/ { NotImplemented, 0, 0}, + /*cmdRestore_Reg*/{ NotImplemented, 0, 0}, + { cmdSetDataBlock, 0, 0}, + { ProcessXor, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessXor, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessXor, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessXor, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessXor, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessXor, destMC, sizeof(COMMAND_HEADER)}, + + { ProcessShl, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessShl, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessShl, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessShl, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessShl, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessShl, destMC, sizeof(COMMAND_HEADER)}, + + { ProcessShr, destRegister, sizeof(COMMAND_HEADER)}, + { ProcessShr, destParamSpace, sizeof(COMMAND_HEADER)}, + { ProcessShr, destWorkSpace, sizeof(COMMAND_HEADER)}, + { ProcessShr, destFrameBuffer, sizeof(COMMAND_HEADER)}, + { ProcessShr, destPLL, sizeof(COMMAND_HEADER)}, + { ProcessShr, destMC, sizeof(COMMAND_HEADER)}, + /*cmdDebug*/ { ProcessDebug, 0, 0}, + { ProcessDS, 0, 0}, + +}; + +// EOF diff --git a/src/AtomBios/Decoder.c b/src/AtomBios/Decoder.c new file mode 100644 index 00000000..95908d5f --- /dev/null +++ b/src/AtomBios/Decoder.c @@ -0,0 +1,235 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + +Module Name: + + Decoder.c + +Abstract: + + Commands Decoder + +Revision History: + + NEG:24.09.2002 Initiated. +--*/ +//#include "AtomBios.h" +#include "Decoder.h" +#include "atombios.h" +#include "CD_binding.h" +#include "CD_Common_Types.h" + +#ifndef DISABLE_EASF + #include "easf.h" +#endif + + + +#define INDIRECT_IO_TABLE (((UINT16)&((ATOM_MASTER_LIST_OF_DATA_TABLES*)0)->IndirectIOAccess)/sizeof(TABLE_UNIT_TYPE) ) +extern COMMANDS_PROPERTIES CallTable[]; + + +UINT8 ProcessCommandProperties(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ + UINT8 opcode=((COMMAND_HEADER*)pParserTempData->pWorkingTableData->IP)->Opcode; + pParserTempData->pWorkingTableData->IP+=CallTable[opcode].headersize; + pParserTempData->ParametersType.Destination=CallTable[opcode].destination; + pParserTempData->ParametersType.Source = pParserTempData->pCmd->Header.Attribute.Source; + pParserTempData->CD_Mask.SrcAlignment=pParserTempData->pCmd->Header.Attribute.SourceAlignment; + pParserTempData->CD_Mask.DestAlignment=pParserTempData->pCmd->Header.Attribute.DestinationAlignment; + return opcode; +} + +UINT16* GetCommandMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) +{ + UINT16 *MasterTableOffset; +#ifndef DISABLE_EASF + if (pDeviceData->format == TABLE_FORMAT_EASF) + { + /* + make MasterTableOffset point to EASF_ASIC_SETUP_TABLE structure, including usSize. + */ + MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset); + } else +#endif + { +#ifndef UEFI_BUILD + MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image); + MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset + pDeviceData->pBIOS_Image ); + MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_COMMAND_TABLE *)MasterTableOffset)->ListOfCommandTables); +#else + MasterTableOffset = (UINT16 *)(&(GetCommandMasterTable( )->ListOfCommandTables)); +#endif + } + return MasterTableOffset; +} + +UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) +{ + UINT16 *MasterTableOffset; + +#ifndef UEFI_BUILD + MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image); + MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset + pDeviceData->pBIOS_Image ); + MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_DATA_TABLE *)MasterTableOffset)->ListOfDataTables); +#else + MasterTableOffset = (UINT16 *)(&(GetDataMasterTable( )->ListOfDataTables)); +#endif + return MasterTableOffset; +} + + +UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable) +{ +#ifndef DISABLE_EASF + UINT16 i; + if ( pParserTempData->pDeviceData->format == TABLE_FORMAT_EASF) + { +/* + Consider EASF_ASIC_SETUP_TABLE structure pointed by pParserTempData->pCmd as UINT16[] + ((UINT16*)pParserTempData->pCmd)[0] = EASF_ASIC_SETUP_TABLE.usSize; + ((UINT16*)pParserTempData->pCmd)[1+n*4] = usFunctionID; + usFunctionID has to be shifted left by 2 before compare it to the value provided by caller. +*/ + for (i=1; (i < ((UINT16*)pParserTempData->pCmd)[0] >> 1);i+=4) + if ((UINT8)(((UINT16*)pParserTempData->pCmd)[i] << 2)==(IndexInMasterTable & EASF_TABLE_INDEX_MASK)) return (i+1+(IndexInMasterTable & EASF_TABLE_ATTR_MASK)); + return 1; + } else +#endif + { + return IndexInMasterTable; + } +} + +CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTable) +{ + PARSER_TEMP_DATA ParserTempData; + WORKING_TABLE_DATA STACK_BASED* prevWorkingTableData; + + ParserTempData.pDeviceData=(DEVICE_DATA*)pDeviceData; +#ifndef DISABLE_EASF + if (pDeviceData->format == TABLE_FORMAT_EASF) + { + ParserTempData.IndirectIOTablePointer = 0; + } else +#endif + { + ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetDataMasterTablePointer(pDeviceData); + ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE]) + pDeviceData->pBIOS_Image); + ParserTempData.IndirectIOTablePointer+=sizeof(ATOM_COMMON_TABLE_HEADER); + } + + ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetCommandMasterTablePointer(pDeviceData); + IndexInMasterTable=GetTrueIndexInMasterTable((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData,IndexInMasterTable); + if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0 ) // if the offset is not ZERO + { + ParserTempData.CommandSpecific.IndexInMasterTable=IndexInMasterTable; + ParserTempData.Multipurpose.CurrentPort=ATI_RegsPort; + ParserTempData.CurrentPortID=INDIRECT_IO_MM; + ParserTempData.CurrentRegBlock=0; + ParserTempData.CurrentFB_Window=0; + prevWorkingTableData=NULL; + ParserTempData.Status=CD_CALL_TABLE; + + do{ + + if (ParserTempData.Status==CD_CALL_TABLE) + { + IndexInMasterTable=ParserTempData.CommandSpecific.IndexInMasterTable; + if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0) // if the offset is not ZERO + { +#ifndef UEFI_BUILD + ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, + ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); +#else + ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, + ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); +#endif + if (ParserTempData.pWorkingTableData!=NULL) + { + ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA)); +#ifndef UEFI_BUILD + ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image); +#else + ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]); +#endif + ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER); + ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData; + prevWorkingTableData=ParserTempData.pWorkingTableData; + ParserTempData.Status = CD_SUCCESS; + } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR; + } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND; + } + if (!CD_ERROR(ParserTempData.Status)) + { + ParserTempData.Status = CD_SUCCESS; + while (!CD_ERROR_OR_COMPLETED(ParserTempData.Status)) + { + + if (IS_COMMAND_VALID(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) + { + ParserTempData.pCmd = (GENERIC_ATTRIBUTE_COMMAND*)ParserTempData.pWorkingTableData->IP; + + if (IS_END_OF_TABLE(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) + { + ParserTempData.Status=CD_COMPLETED; + prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData; + + FreeWorkSpace(pDeviceData, ParserTempData.pWorkingTableData); + ParserTempData.pWorkingTableData=prevWorkingTableData; + if (prevWorkingTableData!=NULL) + { + ParserTempData.pDeviceData->pParameterSpace-= + (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)ParserTempData.pWorkingTableData-> + pTableHead)->TableAttribute.PS_SizeInBytes>>2); + } + // if there is a parent table where to return, then restore PS_pointer to the original state + } + else + { + IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); + (*CallTable[IndexInMasterTable].function)((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); +#if (PARSER_TYPE!=DRIVER_TYPE_PARSER) + BIOS_STACK_MODIFIER(); +#endif + } + } + else + { + ParserTempData.Status=CD_INVALID_OPCODE; + break; + } + + } // while + } // if + else + break; + } while (prevWorkingTableData!=NULL); + if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS; + return ParserTempData.Status; + } else return CD_SUCCESS; +} + +// EOF + diff --git a/src/AtomBios/hwserv_drv.c b/src/AtomBios/hwserv_drv.c new file mode 100644 index 00000000..a5f5a5b8 --- /dev/null +++ b/src/AtomBios/hwserv_drv.c @@ -0,0 +1,348 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + +Module Name: + + hwserv_drv.c + +Abstract: + + Functions defined in the Command Decoder Specification document + +Revision History: + + NEG:27.09.2002 Initiated. +--*/ +#include "CD_binding.h" +#include "CD_hw_services.h" + +//trace settings +#if DEBUG_OUTPUT_DEVICE & 1 + #define TRACE_USING_STDERR //define it to use stderr as trace output, +#endif +#if DEBUG_OUTPUT_DEVICE & 2 + #define TRACE_USING_RS232 +#endif +#if DEBUG_OUTPUT_DEVICE & 4 + #define TRACE_USING_LPT +#endif + + +#if DEBUG_PARSER == 4 + #define IO_TRACE //IO access trace switch, undefine it to turn off + #define PCI_TRACE //PCI access trace switch, undefine it to turn off + #define MEM_TRACE //MEM access trace switch, undefine it to turn off +#endif + +UINT32 CailReadATIRegister(VOID*,UINT32); +VOID CailWriteATIRegister(VOID*,UINT32,UINT32); +VOID* CailAllocateMemory(VOID*,UINT16); +VOID CailReleaseMemory(VOID *,VOID *); +VOID CailDelayMicroSeconds(VOID *,UINT32 ); +VOID CailReadPCIConfigData(VOID*,VOID*,UINT32,UINT16); +VOID CailWritePCIConfigData(VOID*,VOID*,UINT32,UINT16); +UINT32 CailReadFBData(VOID*,UINT32); +VOID CailWriteFBData(VOID*,UINT32,UINT32); +ULONG CailReadPLL(VOID *Context ,ULONG Address); +VOID CailWritePLL(VOID *Context,ULONG Address,ULONG Data); +ULONG CailReadMC(VOID *Context ,ULONG Address); +VOID CailWriteMC(VOID *Context ,ULONG Address,ULONG Data); + + +#if DEBUG_PARSER>0 +VOID CailVideoDebugPrint(VOID*,ULONG_PTR, UINT16); +#endif +// Delay function +#if ( defined ENABLE_PARSER_DELAY || defined ENABLE_ALL_SERVICE_FUNCTIONS ) + +VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32*1000); +} + +VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32); +} +#endif + +VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ +} + +VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +{ +} + + +// PCI READ Access + +#if ( defined ENABLE_PARSER_PCIREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + UINT8 rvl; + CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT8)); + return rvl; +} +#endif + + +#if ( defined ENABLE_PARSER_PCIREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + + UINT16 rvl; + CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT16)); + return rvl; + +} +#endif + + + +#if ( defined ENABLE_PARSER_PCIREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +UINT32 ReadPCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + + UINT32 rvl; + CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT32)); + return rvl; +} +#endif + + +// PCI WRITE Access + +#if ( defined ENABLE_PARSER_PCIWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +VOID WritePCIReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + + CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT8)); + +} + +#endif + + +#if ( defined ENABLE_PARSER_PCIWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +VOID WritePCIReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + + CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT16)); +} + +#endif + + +#if ( defined ENABLE_PARSER_PCIWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +VOID WritePCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT32)); +} +#endif + + + + +// System IO Access +#if ( defined ENABLE_PARSER_SYS_IOREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +UINT8 ReadSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + UINT8 rvl; + rvl=0; + //rvl= (UINT8) ReadGenericPciCfg(dev,reg,sizeof(UINT8)); + return rvl; +} +#endif + + +#if ( defined ENABLE_PARSER_SYS_IOREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + + UINT16 rvl; + rvl=0; + //rvl= (UINT16) ReadGenericPciCfg(dev,reg,sizeof(UINT16)); + return rvl; + +} +#endif + + + +#if ( defined ENABLE_PARSER_SYS_IOREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +UINT32 ReadSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + + UINT32 rvl; + rvl=0; + //rvl= (UINT32) ReadGenericPciCfg(dev,reg,sizeof(UINT32)); + return rvl; +} +#endif + + +// PCI WRITE Access + +#if ( defined ENABLE_PARSER_SYS_IOWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +VOID WriteSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + + //WriteGenericPciCfg(dev,reg,sizeof(UINT8),(UINT32)value); +} + +#endif + + +#if ( defined ENABLE_PARSER_SYS_IOWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +VOID WriteSysIOReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + + //WriteGenericPciCfg(dev,reg,sizeof(UINT16),(UINT32)value); +} + +#endif + + +#if ( defined ENABLE_PARSER_SYS_IOWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +VOID WriteSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + //WriteGenericPciCfg(dev,reg,sizeof(UINT32),(UINT32)value); +} +#endif + +// ATI Registers Memory Mapped Access + +#if ( defined ENABLE_PARSER_REGISTERS_MEMORY_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS) + +UINT32 ReadReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); +} + +VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,(UINT16)pWorkingTableData->Index,pWorkingTableData->DestData32 ); +} + + +VOID ReadIndReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)); +} + +VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1),pWorkingTableData->IndirectData ); +} + +#endif + +// ATI Registers IO Mapped Access + +#if ( defined ENABLE_PARSER_REGISTERS_IO_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS ) +UINT32 ReadRegIO (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + //return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); + return 0; +} +VOID WriteRegIO(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + // return CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32 ); +} +#endif + +// access to Frame buffer, dummy function, need more information to implement it +UINT32 ReadFrameBuffer32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + + return CailReadFBData(pWorkingTableData->pDeviceData->CAIL, (pWorkingTableData->Index <<2 )); + +} + +VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + CailWriteFBData(pWorkingTableData->pDeviceData->CAIL,(pWorkingTableData->Index <<2), pWorkingTableData->DestData32); + +} + + +VOID *AllocateMemory(DEVICE_DATA *pDeviceData , UINT16 MemSize) +{ + if(MemSize) + return(CailAllocateMemory(pDeviceData->CAIL,MemSize)); + else + return NULL; +} + + +VOID ReleaseMemory(DEVICE_DATA *pDeviceData , WORKING_TABLE_DATA* pWorkingTableData) +{ + if( pWorkingTableData) + CailReleaseMemory(pDeviceData->CAIL, pWorkingTableData); +} + + +UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + UINT32 ReadData; + ReadData=(UINT32)CailReadMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); + return ReadData; +} + +VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + CailWriteMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32); +} + +UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + UINT32 ReadData; + ReadData=(UINT32)CailReadPLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); + return ReadData; + +} + +VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) +{ + CailWritePLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32); + +} + + + +#if DEBUG_PARSER>0 +VOID CD_print_string (DEVICE_DATA *pDeviceData, UINT8 *str) +{ + CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR) str, PARSER_STRINGS); +} + +VOID CD_print_value (DEVICE_DATA *pDeviceData, ULONG_PTR value, UINT16 value_type ) +{ + CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR)value, value_type); +} + +#endif + +// EOF diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h new file mode 100644 index 00000000..7a0f27f0 --- /dev/null +++ b/src/AtomBios/includes/CD_Common_Types.h @@ -0,0 +1,150 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/*++ + +Module Name: + + CD_Common_Types.h + +Abstract: + + Defines common data types to use across platforms/SW components + +Revision History: + + NEG:17.09.2002 Initiated. +--*/ +#ifndef _COMMON_TYPES_H_ + #define _COMMON_TYPES_H_ + + #ifndef LINUX + #if _MSC_EXTENSIONS + + // + // use Microsoft* C complier dependent interger width types + // + // typedef unsigned __int64 uint64_t; + // typedef __int64 int64_t; + typedef unsigned __int32 uint32_t; + typedef __int32 int32_t; +#elif defined (linux) || defined (__NetBSD__) + typedef unsigned int uint32_t; + typedef int int32_t; + #else + typedef unsigned long uint32_t; + typedef signed long int32_t; + #endif + typedef unsigned char uint8_t; + typedef signed char int8_t; + typedef unsigned short uint16_t; + typedef signed short int16_t; + #endif +#ifndef UEFI_BUILD + typedef signed int intn_t; + typedef unsigned int uintn_t; +#else +#ifndef EFIX64 + typedef signed int intn_t; + typedef unsigned int uintn_t; +#endif +#endif +#ifndef FGL_LINUX +#pragma warning ( disable : 4142 ) +#endif + + +#ifndef VOID +typedef void VOID; +#endif +#ifndef UEFI_BUILD + typedef intn_t INTN; + typedef uintn_t UINTN; +#else +#ifndef EFIX64 + typedef intn_t INTN; + typedef uintn_t UINTN; +#endif +#endif +#ifndef BOOLEAN +typedef uint8_t BOOLEAN; +#endif +#ifndef INT8 +typedef int8_t INT8; +#endif +#ifndef UINT8 +typedef uint8_t UINT8; +#endif +#ifndef INT16 +typedef int16_t INT16; +#endif +#ifndef UINT16 +typedef uint16_t UINT16; +#endif +#ifndef INT32 +typedef int32_t INT32; +#endif +#ifndef UINT32 +typedef uint32_t UINT32; +#endif +//typedef int64_t INT64; +//typedef uint64_t UINT64; +typedef uint8_t CHAR8; +typedef uint16_t CHAR16; +#ifndef USHORT +typedef UINT16 USHORT; +#endif +#ifndef UCHAR +typedef UINT8 UCHAR; +#endif +#ifndef ULONG +typedef UINT32 ULONG; +#endif + +#ifndef _WIN64 +#ifndef ULONG_PTR +typedef unsigned long ULONG_PTR; +#endif // ULONG_PTR +#endif // _WIN64 + +//#define FAR __far +#ifndef TRUE + #define TRUE ((BOOLEAN) 1 == 1) +#endif + +#ifndef FALSE + #define FALSE ((BOOLEAN) 0 == 1) +#endif + +#ifndef NULL + #define NULL ((VOID *) 0) +#endif + +//typedef UINTN CD_STATUS; + + +#ifndef FGL_LINUX +#pragma warning ( default : 4142 ) +#endif +#endif // _COMMON_TYPES_H_ + +// EOF diff --git a/src/AtomBios/includes/CD_Definitions.h b/src/AtomBios/includes/CD_Definitions.h new file mode 100644 index 00000000..98fd4954 --- /dev/null +++ b/src/AtomBios/includes/CD_Definitions.h @@ -0,0 +1,49 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/*++ + +Module Name: + +CD_Definitions.h + +Abstract: + +Defines Script Language commands + +Revision History: + +NEG:27.08.2002 Initiated. +--*/ + +#include "CD_Structs.h" +#ifndef _CD_DEFINITIONS_H +#define _CD_DEFINITIONS_H_ +#ifdef DRIVER_PARSER +VOID *AllocateMemory(VOID *, UINT16); +VOID ReleaseMemory(DEVICE_DATA * , WORKING_TABLE_DATA* ); +#endif +CD_STATUS ParseTable(DEVICE_DATA* pDeviceData, UINT8 IndexInMasterTable); +//CD_STATUS CD_MainLoop(PARSER_TEMP_DATA_POINTER pParserTempData); +CD_STATUS Main_Loop(DEVICE_DATA* pDeviceData,UINT16 *MasterTableOffset,UINT8 IndexInMasterTable); +UINT16* GetCommandMasterTablePointer(DEVICE_DATA* pDeviceData); +#endif //CD_DEFINITIONS diff --git a/src/AtomBios/includes/CD_Opcodes.h b/src/AtomBios/includes/CD_Opcodes.h new file mode 100644 index 00000000..2f3bec5f --- /dev/null +++ b/src/AtomBios/includes/CD_Opcodes.h @@ -0,0 +1,181 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/*++ + +Module Name: + +CD_OPCODEs.h + +Abstract: + +Defines Command Decoder OPCODEs + +Revision History: + +NEG:24.09.2002 Initiated. +--*/ +#ifndef _CD_OPCODES_H_ +#define _CD_OPCODES_H_ + +typedef enum _OPCODE { + Reserved_00= 0, // 0 = 0x00 + // MOVE_ group + MOVE_REG_OPCODE, // 1 = 0x01 + FirstValidCommand=MOVE_REG_OPCODE, + MOVE_PS_OPCODE, // 2 = 0x02 + MOVE_WS_OPCODE, // 3 = 0x03 + MOVE_FB_OPCODE, // 4 = 0x04 + MOVE_PLL_OPCODE, // 5 = 0x05 + MOVE_MC_OPCODE, // 6 = 0x06 + // Logic group + AND_REG_OPCODE, // 7 = 0x07 + AND_PS_OPCODE, // 8 = 0x08 + AND_WS_OPCODE, // 9 = 0x09 + AND_FB_OPCODE, // 10 = 0x0A + AND_PLL_OPCODE, // 11 = 0x0B + AND_MC_OPCODE, // 12 = 0x0C + OR_REG_OPCODE, // 13 = 0x0D + OR_PS_OPCODE, // 14 = 0x0E + OR_WS_OPCODE, // 15 = 0x0F + OR_FB_OPCODE, // 16 = 0x10 + OR_PLL_OPCODE, // 17 = 0x11 + OR_MC_OPCODE, // 18 = 0x12 + SHIFT_LEFT_REG_OPCODE, // 19 = 0x13 + SHIFT_LEFT_PS_OPCODE, // 20 = 0x14 + SHIFT_LEFT_WS_OPCODE, // 21 = 0x15 + SHIFT_LEFT_FB_OPCODE, // 22 = 0x16 + SHIFT_LEFT_PLL_OPCODE, // 23 = 0x17 + SHIFT_LEFT_MC_OPCODE, // 24 = 0x18 + SHIFT_RIGHT_REG_OPCODE, // 25 = 0x19 + SHIFT_RIGHT_PS_OPCODE, // 26 = 0x1A + SHIFT_RIGHT_WS_OPCODE, // 27 = 0x1B + SHIFT_RIGHT_FB_OPCODE, // 28 = 0x1C + SHIFT_RIGHT_PLL_OPCODE, // 29 = 0x1D + SHIFT_RIGHT_MC_OPCODE, // 30 = 0x1E + // Arithmetic group + MUL_REG_OPCODE, // 31 = 0x1F + MUL_PS_OPCODE, // 32 = 0x20 + MUL_WS_OPCODE, // 33 = 0x21 + MUL_FB_OPCODE, // 34 = 0x22 + MUL_PLL_OPCODE, // 35 = 0x23 + MUL_MC_OPCODE, // 36 = 0x24 + DIV_REG_OPCODE, // 37 = 0x25 + DIV_PS_OPCODE, // 38 = 0x26 + DIV_WS_OPCODE, // 39 = 0x27 + DIV_FB_OPCODE, // 40 = 0x28 + DIV_PLL_OPCODE, // 41 = 0x29 + DIV_MC_OPCODE, // 42 = 0x2A + ADD_REG_OPCODE, // 43 = 0x2B + ADD_PS_OPCODE, // 44 = 0x2C + ADD_WS_OPCODE, // 45 = 0x2D + ADD_FB_OPCODE, // 46 = 0x2E + ADD_PLL_OPCODE, // 47 = 0x2F + ADD_MC_OPCODE, // 48 = 0x30 + SUB_REG_OPCODE, // 49 = 0x31 + SUB_PS_OPCODE, // 50 = 0x32 + SUB_WS_OPCODE, // 51 = 0x33 + SUB_FB_OPCODE, // 52 = 0x34 + SUB_PLL_OPCODE, // 53 = 0x35 + SUB_MC_OPCODE, // 54 = 0x36 + // Control grouop + SET_ATI_PORT_OPCODE, // 55 = 0x37 + SET_PCI_PORT_OPCODE, // 56 = 0x38 + SET_SYS_IO_PORT_OPCODE, // 57 = 0x39 + SET_REG_BLOCK_OPCODE, // 58 = 0x3A + SET_FB_BASE_OPCODE, // 59 = 0x3B + COMPARE_REG_OPCODE, // 60 = 0x3C + COMPARE_PS_OPCODE, // 61 = 0x3D + COMPARE_WS_OPCODE, // 62 = 0x3E + COMPARE_FB_OPCODE, // 63 = 0x3F + COMPARE_PLL_OPCODE, // 64 = 0x40 + COMPARE_MC_OPCODE, // 65 = 0x41 + SWITCH_OPCODE, // 66 = 0x42 + JUMP__OPCODE, // 67 = 0x43 + JUMP_EQUAL_OPCODE, // 68 = 0x44 + JUMP_BELOW_OPCODE, // 69 = 0x45 + JUMP_ABOVE_OPCODE, // 70 = 0x46 + JUMP_BELOW_OR_EQUAL_OPCODE, // 71 = 0x47 + JUMP_ABOVE_OR_EQUAL_OPCODE, // 72 = 0x48 + JUMP_NOT_EQUAL_OPCODE, // 73 = 0x49 + TEST_REG_OPCODE, // 74 = 0x4A + TEST_PS_OPCODE, // 75 = 0x4B + TEST_WS_OPCODE, // 76 = 0x4C + TEST_FB_OPCODE, // 77 = 0x4D + TEST_PLL_OPCODE, // 78 = 0x4E + TEST_MC_OPCODE, // 79 = 0x4F + DELAY_MILLISEC_OPCODE, // 80 = 0x50 + DELAY_MICROSEC_OPCODE, // 81 = 0x51 + CALL_TABLE_OPCODE, // 82 = 0x52 + REPEAT_OPCODE, // 83 = 0x53 + // Miscellaneous group + CLEAR_REG_OPCODE, // 84 = 0x54 + CLEAR_PS_OPCODE, // 85 = 0x55 + CLEAR_WS_OPCODE, // 86 = 0x56 + CLEAR_FB_OPCODE, // 87 = 0x57 + CLEAR_PLL_OPCODE, // 88 = 0x58 + CLEAR_MC_OPCODE, // 89 = 0x59 + NOP_OPCODE, // 90 = 0x5A + EOT_OPCODE, // 91 = 0x5B + MASK_REG_OPCODE, // 92 = 0x5C + MASK_PS_OPCODE, // 93 = 0x5D + MASK_WS_OPCODE, // 94 = 0x5E + MASK_FB_OPCODE, // 95 = 0x5F + MASK_PLL_OPCODE, // 96 = 0x60 + MASK_MC_OPCODE, // 97 = 0x61 + // BIOS dedicated group + POST_CARD_OPCODE, // 98 = 0x62 + BEEP_OPCODE, // 99 = 0x63 + SAVE_REG_OPCODE, // 100 = 0x64 + RESTORE_REG_OPCODE, // 101 = 0x65 + SET_DATA_BLOCK_OPCODE, // 102 = 0x66 + + XOR_REG_OPCODE, // 103 = 0x67 + XOR_PS_OPCODE, // 104 = 0x68 + XOR_WS_OPCODE, // 105 = 0x69 + XOR_FB_OPCODE, // 106 = 0x6a + XOR_PLL_OPCODE, // 107 = 0x6b + XOR_MC_OPCODE, // 108 = 0x6c + + SHL_REG_OPCODE, // 109 = 0x6d + SHL_PS_OPCODE, // 110 = 0x6e + SHL_WS_OPCODE, // 111 = 0x6f + SHL_FB_OPCODE, // 112 = 0x70 + SHL_PLL_OPCODE, // 113 = 0x71 + SHL_MC_OPCODE, // 114 = 0x72 + + SHR_REG_OPCODE, // 115 = 0x73 + SHR_PS_OPCODE, // 116 = 0x74 + SHR_WS_OPCODE, // 117 = 0x75 + SHR_FB_OPCODE, // 118 = 0x76 + SHR_PLL_OPCODE, // 119 = 0x77 + SHR_MC_OPCODE, // 120 = 0x78 + + DEBUG_OPCODE, // 121 = 0x79 + CTB_DS_OPCODE, // 122 = 0x7A + + LastValidCommand = CTB_DS_OPCODE, + // Extension specificaTOR + Extension = 0x80, // 128 = 0x80 // Next byte is an OPCODE as well + Reserved_FF = 255 // 255 = 0xFF +}OPCODE; +#endif // _CD_OPCODES_H_ diff --git a/src/AtomBios/includes/CD_Structs.h b/src/AtomBios/includes/CD_Structs.h new file mode 100644 index 00000000..c43f81db --- /dev/null +++ b/src/AtomBios/includes/CD_Structs.h @@ -0,0 +1,464 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/*++ + +Module Name: + +CD_Struct.h + +Abstract: + +Defines Script Language commands + +Revision History: + +NEG:26.08.2002 Initiated. +--*/ + +#include "CD_binding.h" +#ifndef _CD_STRUCTS_H_ +#define _CD_STRUCTS_H_ + +#ifdef UEFI_BUILD +typedef UINT16** PTABLE_UNIT_TYPE; +typedef UINTN TABLE_UNIT_TYPE; +#else +typedef UINT16* PTABLE_UNIT_TYPE; +typedef UINT16 TABLE_UNIT_TYPE; +#endif + +#include <regsdef.h> //This important file is dynamically generated based on the ASIC!!!! + +#define PARSER_MAJOR_REVISION 5 +#define PARSER_MINOR_REVISION 0 + +//#include "atombios.h" +#if (PARSER_TYPE==DRIVER_TYPE_PARSER) +#ifdef FGL_LINUX +#pragma pack(push,1) +#else +#pragma pack(push) +#pragma pack(1) +#endif +#endif + +#include "CD_Common_Types.h" +#include "CD_Opcodes.h" +typedef UINT16 WORK_SPACE_SIZE; +typedef enum _CD_STATUS{ + CD_SUCCESS, + CD_CALL_TABLE, + CD_COMPLETED=0x10, + CD_GENERAL_ERROR=0x80, + CD_INVALID_OPCODE, + CD_NOT_IMPLEMENTED, + CD_EXEC_TABLE_NOT_FOUND, + CD_EXEC_PARAMETER_ERROR, + CD_EXEC_PARSER_ERROR, + CD_INVALID_DESTINATION_TYPE, + CD_UNEXPECTED_BEHAVIOR, + CD_INVALID_SWITCH_OPERAND_SIZE +}CD_STATUS; + +#define PARSER_STRINGS 0 +#define PARSER_DEC 1 +#define PARSER_HEX 2 + +#define DB_CURRENT_COMMAND_TABLE 0xFF + +#define TABLE_FORMAT_BIOS 0 +#define TABLE_FORMAT_EASF 1 + +#define EASF_TABLE_INDEX_MASK 0xfc +#define EASF_TABLE_ATTR_MASK 0x03 + +#define CD_ERROR(a) (((INTN) (a)) > CD_COMPLETED) +#define CD_ERROR_OR_COMPLETED(a) (((INTN) (a)) > CD_SUCCESS) + + +#if (BIOS_PARSER==1) +#ifdef _H2INC +#define STACK_BASED +#else +extern __segment farstack; +#define STACK_BASED __based(farstack) +#endif +#else +#define STACK_BASED +#endif + +typedef enum _COMPARE_FLAGS{ + Below, + Equal, + Above, + NotEqual, + Overflow, + NoCondition +}COMPARE_FLAGS; + +typedef UINT16 IO_BASE_ADDR; + +typedef struct _BUS_DEV_FUNC_PCI_ADDR{ + UINT8 Register; + UINT8 Function; + UINT8 Device; + UINT8 Bus; +} BUS_DEV_FUNC_PCI_ADDR; + +typedef struct _BUS_DEV_FUNC{ + UINT8 Function : 3; + UINT8 Device : 5; + UINT8 Bus; +} BUS_DEV_FUNC; + +#ifndef UEFI_BUILD +typedef struct _PCI_CONFIG_ACCESS_CF8{ + UINT32 Reg : 8; + UINT32 Func : 3; + UINT32 Dev : 5; + UINT32 Bus : 8; + UINT32 Reserved: 7; + UINT32 Enable : 1; +} PCI_CONFIG_ACCESS_CF8; +#endif + +typedef enum _MEM_RESOURCE { + Stack_Resource, + FrameBuffer_Resource, + BIOS_Image_Resource +}MEM_RESOURCE; + +typedef enum _PORTS{ + ATI_RegsPort, + PCI_Port, + SystemIO_Port +}PORTS; + +typedef enum _OPERAND_TYPE { + typeRegister, + typeParamSpace, + typeWorkSpace, + typeFrameBuffer, + typeIndirect, + typeDirect, + typePLL, + typeMC +}OPERAND_TYPE; + +typedef enum _DESTINATION_OPERAND_TYPE { + destRegister, + destParamSpace, + destWorkSpace, + destFrameBuffer, + destPLL, + destMC +}DESTINATION_OPERAND_TYPE; + +typedef enum _SOURCE_OPERAND_TYPE { + sourceRegister, + sourceParamSpace, + sourceWorkSpace, + sourceFrameBuffer, + sourceIndirect, + sourceDirect, + sourcePLL, + sourceMC +}SOURCE_OPERAND_TYPE; + +typedef enum _ALIGNMENT_TYPE { + alignmentDword, + alignmentLowerWord, + alignmentMiddleWord, + alignmentUpperWord, + alignmentByte0, + alignmentByte1, + alignmentByte2, + alignmentByte3 +}ALIGNMENT_TYPE; + + +#define INDIRECT_IO_READ 0 +#define INDIRECT_IO_WRITE 0x80 +#define INDIRECT_IO_MM 0 +#define INDIRECT_IO_PLL 1 +#define INDIRECT_IO_MC 2 + +typedef struct _PARAMETERS_TYPE{ + UINT8 Destination; + UINT8 Source; +}PARAMETERS_TYPE; +/* The following structures don't used to allocate any type of objects(variables). + they are serve the only purpose: Get proper access to data(commands), found in the tables*/ +typedef struct _PA_BYTE_BYTE{ + UINT8 PA_Destination; + UINT8 PA_Source; + UINT8 PA_Padding[8]; +}PA_BYTE_BYTE; +typedef struct _PA_BYTE_WORD{ + UINT8 PA_Destination; + UINT16 PA_Source; + UINT8 PA_Padding[7]; +}PA_BYTE_WORD; +typedef struct _PA_BYTE_DWORD{ + UINT8 PA_Destination; + UINT32 PA_Source; + UINT8 PA_Padding[5]; +}PA_BYTE_DWORD; +typedef struct _PA_WORD_BYTE{ + UINT16 PA_Destination; + UINT8 PA_Source; + UINT8 PA_Padding[7]; +}PA_WORD_BYTE; +typedef struct _PA_WORD_WORD{ + UINT16 PA_Destination; + UINT16 PA_Source; + UINT8 PA_Padding[6]; +}PA_WORD_WORD; +typedef struct _PA_WORD_DWORD{ + UINT16 PA_Destination; + UINT32 PA_Source; + UINT8 PA_Padding[4]; +}PA_WORD_DWORD; +typedef struct _PA_WORD_XX{ + UINT16 PA_Destination; + UINT8 PA_Padding[8]; +}PA_WORD_XX; +typedef struct _PA_BYTE_XX{ + UINT8 PA_Destination; + UINT8 PA_Padding[9]; +}PA_BYTE_XX; +/*The following 6 definitions used for Mask operation*/ +typedef struct _PA_BYTE_BYTE_BYTE{ + UINT8 PA_Destination; + UINT8 PA_AndMaskByte; + UINT8 PA_OrMaskByte; + UINT8 PA_Padding[7]; +}PA_BYTE_BYTE_BYTE; +typedef struct _PA_BYTE_WORD_WORD{ + UINT8 PA_Destination; + UINT16 PA_AndMaskWord; + UINT16 PA_OrMaskWord; + UINT8 PA_Padding[5]; +}PA_BYTE_WORD_WORD; +typedef struct _PA_BYTE_DWORD_DWORD{ + UINT8 PA_Destination; + UINT32 PA_AndMaskDword; + UINT32 PA_OrMaskDword; + UINT8 PA_Padding; +}PA_BYTE_DWORD_DWORD; +typedef struct _PA_WORD_BYTE_BYTE{ + UINT16 PA_Destination; + UINT8 PA_AndMaskByte; + UINT8 PA_OrMaskByte; + UINT8 PA_Padding[6]; +}PA_WORD_BYTE_BYTE; +typedef struct _PA_WORD_WORD_WORD{ + UINT16 PA_Destination; + UINT16 PA_AndMaskWord; + UINT16 PA_OrMaskWord; + UINT8 PA_Padding[4]; +}PA_WORD_WORD_WORD; +typedef struct _PA_WORD_DWORD_DWORD{ + UINT16 PA_Destination; + UINT32 PA_AndMaskDword; + UINT32 PA_OrMaskDword; +}PA_WORD_DWORD_DWORD; + + +typedef union _PARAMETER_ACCESS { + PA_BYTE_XX ByteXX; + PA_BYTE_BYTE ByteByte; + PA_BYTE_WORD ByteWord; + PA_BYTE_DWORD ByteDword; + PA_WORD_BYTE WordByte; + PA_WORD_WORD WordWord; + PA_WORD_DWORD WordDword; + PA_WORD_XX WordXX; +/*The following 6 definitions used for Mask operation*/ + PA_BYTE_BYTE_BYTE ByteByteAndByteOr; + PA_BYTE_WORD_WORD ByteWordAndWordOr; + PA_BYTE_DWORD_DWORD ByteDwordAndDwordOr; + PA_WORD_BYTE_BYTE WordByteAndByteOr; + PA_WORD_WORD_WORD WordWordAndWordOr; + PA_WORD_DWORD_DWORD WordDwordAndDwordOr; +}PARAMETER_ACCESS; + +typedef struct _COMMAND_ATTRIBUTE { + UINT8 Source:3; + UINT8 SourceAlignment:3; + UINT8 DestinationAlignment:2; +}COMMAND_ATTRIBUTE; + +typedef struct _SOURCE_DESTINATION_ALIGNMENT{ + UINT8 DestAlignment; + UINT8 SrcAlignment; +}SOURCE_DESTINATION_ALIGNMENT; +typedef struct _MULTIPLICATION_RESULT{ + UINT32 Low32Bit; + UINT32 High32Bit; +}MULTIPLICATION_RESULT; +typedef struct _DIVISION_RESULT{ + UINT32 Quotient32; + UINT32 Reminder32; +}DIVISION_RESULT; +typedef union _DIVISION_MULTIPLICATION_RESULT{ + MULTIPLICATION_RESULT Multiplication; + DIVISION_RESULT Division; +}DIVISION_MULTIPLICATION_RESULT; +typedef struct _COMMAND_HEADER { + UINT8 Opcode; + COMMAND_ATTRIBUTE Attribute; +}COMMAND_HEADER; + +typedef struct _GENERIC_ATTRIBUTE_COMMAND{ + COMMAND_HEADER Header; + PARAMETER_ACCESS Parameters; +} GENERIC_ATTRIBUTE_COMMAND; + +typedef struct _COMMAND_TYPE_1{ + UINT8 Opcode; + PARAMETER_ACCESS Parameters; +} COMMAND_TYPE_1; + +typedef struct _COMMAND_TYPE_OPCODE_OFFSET16{ + UINT8 Opcode; + UINT16 CD_Offset16; +} COMMAND_TYPE_OPCODE_OFFSET16; + +typedef struct _COMMAND_TYPE_OPCODE_OFFSET32{ + UINT8 Opcode; + UINT32 CD_Offset32; +} COMMAND_TYPE_OPCODE_OFFSET32; + +typedef struct _COMMAND_TYPE_OPCODE_VALUE_BYTE{ + UINT8 Opcode; + UINT8 Value; +} COMMAND_TYPE_OPCODE_VALUE_BYTE; + +typedef union _COMMAND_SPECIFIC_UNION{ + UINT8 ContinueSwitch; + UINT8 ControlOperandSourcePosition; + UINT8 IndexInMasterTable; +} COMMAND_SPECIFIC_UNION; + + +typedef struct _CD_GENERIC_BYTE{ + UINT16 CommandType:3; + UINT16 CurrentParameterSize:3; + UINT16 CommandAccessType:3; + UINT16 CurrentPort:2; + UINT16 PS_SizeInDwordsUsedByCallingTable:5; +}CD_GENERIC_BYTE; + +typedef UINT8 COMMAND_TYPE_OPCODE_ONLY; + +typedef UINT8 COMMAND_HEADER_POINTER; + + +#if (PARSER_TYPE==BIOS_TYPE_PARSER) + +typedef struct _DEVICE_DATA { + UINT32 STACK_BASED *pParameterSpace; + UINT8 *pBIOS_Image; + UINT8 format; +#if (IO_INTERFACE==PARSER_INTERFACE) + IO_BASE_ADDR IOBase; +#endif +} DEVICE_DATA; + +#else + +typedef struct _DEVICE_DATA { + UINT32 *pParameterSpace; + VOID *CAIL; + UINT8 *pBIOS_Image; + UINT32 format; +} DEVICE_DATA; + +#endif + +struct _PARSER_TEMP_DATA; +typedef UINT32 WORKSPACE_POINTER; + +struct _WORKING_TABLE_DATA{ + UINT8 * pTableHead; + COMMAND_HEADER_POINTER * IP; // Commands pointer + WORKSPACE_POINTER STACK_BASED * pWorkSpace; + struct _WORKING_TABLE_DATA STACK_BASED * prevWorkingTableData; +}; + + + +typedef struct _PARSER_TEMP_DATA{ + DEVICE_DATA STACK_BASED *pDeviceData; + struct _WORKING_TABLE_DATA STACK_BASED *pWorkingTableData; + UINT32 SourceData32; + UINT32 DestData32; + DIVISION_MULTIPLICATION_RESULT MultiplicationOrDivision; + UINT32 Index; + UINT32 CurrentFB_Window; + UINT32 IndirectData; + UINT16 CurrentRegBlock; + TABLE_UNIT_TYPE CurrentDataBlock; + UINT16 AttributesData; +// UINT8 *IndirectIOTable; + UINT8 *IndirectIOTablePointer; + GENERIC_ATTRIBUTE_COMMAND *pCmd; //CurrentCommand; + SOURCE_DESTINATION_ALIGNMENT CD_Mask; + PARAMETERS_TYPE ParametersType; + CD_GENERIC_BYTE Multipurpose; + UINT8 CompareFlags; + COMMAND_SPECIFIC_UNION CommandSpecific; + CD_STATUS Status; + UINT8 Shift2MaskConverter; + UINT8 CurrentPortID; +} PARSER_TEMP_DATA; + + +typedef struct _WORKING_TABLE_DATA WORKING_TABLE_DATA; + + + +typedef VOID (*COMMANDS_DECODER)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +typedef VOID (*WRITE_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +typedef UINT32 (*READ_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +typedef UINT32 (*CD_GET_PARAMETERS)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + +typedef struct _COMMANDS_PROPERTIES +{ + COMMANDS_DECODER function; + UINT8 destination; + UINT8 headersize; +} COMMANDS_PROPERTIES; + +typedef struct _INDIRECT_IO_PARSER_COMMANDS +{ + COMMANDS_DECODER func; + UINT8 csize; +} INDIRECT_IO_PARSER_COMMANDS; + +#if (PARSER_TYPE==DRIVER_TYPE_PARSER) +#pragma pack(pop) +#endif + +#endif diff --git a/src/AtomBios/includes/CD_binding.h b/src/AtomBios/includes/CD_binding.h new file mode 100644 index 00000000..7b021d3e --- /dev/null +++ b/src/AtomBios/includes/CD_binding.h @@ -0,0 +1,46 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifdef NT_BUILD +#ifdef LH_BUILD +#include <ntddk.h> +#else +#include <miniport.h> +#endif // LH_BUILD +#endif // NT_BUILD + + +#if ((defined DBG) || (defined DEBUG)) +#define DEBUG_PARSER 1 // enable parser debug output +#endif + +#define USE_SWITCH_COMMAND 1 +#define DRIVER_TYPE_PARSER 0x48 + +#define PARSER_TYPE DRIVER_TYPE_PARSER + +#define AllocateWorkSpace(x,y) AllocateMemory(pDeviceData,y) +#define FreeWorkSpace(x,y) ReleaseMemory(x,y) + +#define RELATIVE_TO_BIOS_IMAGE( x ) ((ULONG_PTR)x + (ULONG_PTR)((DEVICE_DATA*)pParserTempData->pDeviceData->pBIOS_Image)) +#define RELATIVE_TO_TABLE( x ) (x + (UCHAR *)(pParserTempData->pWorkingTableData->pTableHead)) + diff --git a/src/AtomBios/includes/CD_hw_services.h b/src/AtomBios/includes/CD_hw_services.h new file mode 100644 index 00000000..529fde59 --- /dev/null +++ b/src/AtomBios/includes/CD_hw_services.h @@ -0,0 +1,318 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _HW_SERVICES_INTERFACE_ +#define _HW_SERVICES_INTERFACE_ + +#include "CD_Common_Types.h" +#include "CD_Structs.h" + + +// CD - from Command Decoder +typedef UINT16 CD_REG_INDEX; +typedef UINT8 CD_PCI_OFFSET; +typedef UINT16 CD_FB_OFFSET; +typedef UINT16 CD_SYS_IO_PORT; +typedef UINT8 CD_MEM_TYPE; +typedef UINT8 CD_MEM_SIZE; + +typedef VOID * CD_VIRT_ADDR; +typedef UINT32 CD_PHYS_ADDR; +typedef UINT32 CD_IO_ADDR; + +/***********************ATI Registers access routines**************************/ + + VOID ReadIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + UINT32 ReadReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + +/************************PCI Registers access routines*************************/ + + UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + UINT32 ReadPCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID WritePCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID WritePCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID WritePCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + +/***************************Frame buffer access routines************************/ + + UINT32 ReadFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + +/******************System IO Registers access routines********************/ + + UINT8 ReadSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + UINT32 ReadSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID WriteSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID WriteSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID WriteSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + +/****************************Delay routines****************************************/ + + VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData); // take WORKING_TABLE_DATA->SourceData32 as a delay value + + VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + + +//************************Tracing/Debugging routines and macroses******************/ +#define KEYPRESSED -1 + +#if (DEBUG_PARSER != 0) + +#ifdef DRIVER_PARSER + +VOID CD_print_string (DEVICE_DATA STACK_BASED *pDeviceData, UINT8 *str); +VOID CD_print_value (DEVICE_DATA STACK_BASED *pDeviceData, ULONG_PTR value, UINT16 value_type ); + +// Level 1 : can use WorkingTableData or pDeviceData +#define CD_TRACE_DL1(string) CD_print_string(pDeviceData, string); +#define CD_TRACETAB_DL1(string) CD_TRACE_DL1("\n");CD_TRACE_DL1(string) +#define CD_TRACEDEC_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_DEC); +#define CD_TRACEHEX_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_HEX); + +// Level 2:can use pWorkingTableData +#define CD_TRACE_DL2(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string); +#define CD_TRACETAB_DL2(string) CD_TRACE_DL2("\n");CD_TRACE_DL2(string) +#define CD_TRACEDEC_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_DEC); +#define CD_TRACEHEX_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_HEX); + +// Level 3:can use pWorkingTableData +#define CD_TRACE_DL3(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string); +#define CD_TRACETAB_DL3(string) CD_TRACE_DL3("\n");CD_TRACE_DL3(string) +#define CD_TRACEDEC_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_DEC); +#define CD_TRACEHEX_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_HEX); + +#define CD_TRACE(string) +#define CD_WAIT(what) +#define CD_BREAKPOINT() + +#else + + +VOID CD_assert (UINT8 *file, INTN lineno); //output file/line to debug console +VOID CD_postcode(UINT8 value); //output post code to debug console +VOID CD_print (UINT8 *str); //output text to debug console +VOID CD_print_dec(UINTN value); //output value in decimal format to debug console +VOID CD_print_hex(UINT32 value, UINT8 len); //output value in hexadecimal format to debug console +VOID CD_print_buf(UINT8 *p, UINTN len); //output dump of memory to debug console +VOID CD_wait(INT32 what); //wait for KEYPRESSED=-1 or Delay value expires +VOID CD_breakpoint(); //insert int3 opcode or 0xF1 (for American Arium) + +#define CD_ASSERT(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) +#define CD_POSTCODE(value) CD_postcode(value) +#define CD_TRACE(string) CD_print(string) +#define CD_TRACETAB(string) CD_print(string) +#define CD_TRACEDEC(value) CD_print_dec( (UINTN)(value)) +#define CD_TRACEHEX(value) CD_print_hex( (UINT32)(value), sizeof(value) ) +#define CD_TRACEBUF(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) +#define CD_WAIT(what) CD_wait((INT32)what) +#define CD_BREAKPOINT() CD_breakpoint() + +#if (DEBUG_PARSER == 4) +#define CD_ASSERT_DL4(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) +#define CD_POSTCODE_DL4(value) CD_postcode(value) +#define CD_TRACE_DL4(string) CD_print(string) +#define CD_TRACETAB_DL4(string) CD_print("\n\t\t");CD_print(string) +#define CD_TRACEDEC_DL4(value) CD_print_dec( (UINTN)(value)) +#define CD_TRACEHEX_DL4(value) CD_print_hex( (UINT32)(value), sizeof(value) ) +#define CD_TRACEBUF_DL4(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) +#define CD_WAIT_DL4(what) CD_wait((INT32)what) +#define CD_BREAKPOINT_DL4() CD_breakpoint() +#else +#define CD_ASSERT_DL4(condition) +#define CD_POSTCODE_DL4(value) +#define CD_TRACE_DL4(string) +#define CD_TRACETAB_DL4(string) +#define CD_TRACEDEC_DL4(value) +#define CD_TRACEHEX_DL4(value) +#define CD_TRACEBUF_DL4(pointer, len) +#define CD_WAIT_DL4(what) +#define CD_BREAKPOINT_DL4() +#endif + +#if (DEBUG_PARSER >= 3) +#define CD_ASSERT_DL3(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) +#define CD_POSTCODE_DL3(value) CD_postcode(value) +#define CD_TRACE_DL3(string) CD_print(string) +#define CD_TRACETAB_DL3(string) CD_print("\n\t\t");CD_print(string) +#define CD_TRACEDEC_DL3(value) CD_print_dec( (UINTN)(value)) +#define CD_TRACEHEX_DL3(value) CD_print_hex( (UINT32)(value), sizeof(value) ) +#define CD_TRACEBUF_DL3(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) +#define CD_WAIT_DL3(what) CD_wait((INT32)what) +#define CD_BREAKPOINT_DL3() CD_breakpoint() +#else +#define CD_ASSERT_DL3(condition) +#define CD_POSTCODE_DL3(value) +#define CD_TRACE_DL3(string) +#define CD_TRACETAB_DL3(string) +#define CD_TRACEDEC_DL3(value) +#define CD_TRACEHEX_DL3(value) +#define CD_TRACEBUF_DL3(pointer, len) +#define CD_WAIT_DL3(what) +#define CD_BREAKPOINT_DL3() +#endif + + +#if (DEBUG_PARSER >= 2) +#define CD_ASSERT_DL2(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) +#define CD_POSTCODE_DL2(value) CD_postcode(value) +#define CD_TRACE_DL2(string) CD_print(string) +#define CD_TRACETAB_DL2(string) CD_print("\n\t");CD_print(string) +#define CD_TRACEDEC_DL2(value) CD_print_dec( (UINTN)(value)) +#define CD_TRACEHEX_DL2(value) CD_print_hex( (UINT32)(value), sizeof(value) ) +#define CD_TRACEBUF_DL2(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) +#define CD_WAIT_DL2(what) CD_wait((INT32)what) +#define CD_BREAKPOINT_DL2() CD_breakpoint() +#else +#define CD_ASSERT_DL2(condition) +#define CD_POSTCODE_DL2(value) +#define CD_TRACE_DL2(string) +#define CD_TRACETAB_DL2(string) +#define CD_TRACEDEC_DL2(value) +#define CD_TRACEHEX_DL2(value) +#define CD_TRACEBUF_DL2(pointer, len) +#define CD_WAIT_DL2(what) +#define CD_BREAKPOINT_DL2() +#endif + + +#if (DEBUG_PARSER >= 1) +#define CD_ASSERT_DL1(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) +#define CD_POSTCODE_DL1(value) CD_postcode(value) +#define CD_TRACE_DL1(string) CD_print(string) +#define CD_TRACETAB_DL1(string) CD_print("\n");CD_print(string) +#define CD_TRACEDEC_DL1(value) CD_print_dec( (UINTN)(value)) +#define CD_TRACEHEX_DL1(value) CD_print_hex( (UINT32)(value), sizeof(value) ) +#define CD_TRACEBUF_DL1(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) +#define CD_WAIT_DL1(what) CD_wait((INT32)what) +#define CD_BREAKPOINT_DL1() CD_breakpoint() +#else +#define CD_ASSERT_DL1(condition) +#define CD_POSTCODE_DL1(value) +#define CD_TRACE_DL1(string) +#define CD_TRACETAB_DL1(string) +#define CD_TRACEDEC_DL1(value) +#define CD_TRACEHEX_DL1(value) +#define CD_TRACEBUF_DL1(pointer, len) +#define CD_WAIT_DL1(what) +#define CD_BREAKPOINT_DL1() +#endif + +#endif //#ifdef DRIVER_PARSER + + +#else + +#define CD_ASSERT(condition) +#define CD_POSTCODE(value) +#define CD_TRACE(string) +#define CD_TRACEDEC(value) +#define CD_TRACEHEX(value) +#define CD_TRACEBUF(pointer, len) +#define CD_WAIT(what) +#define CD_BREAKPOINT() + +#define CD_ASSERT_DL4(condition) +#define CD_POSTCODE_DL4(value) +#define CD_TRACE_DL4(string) +#define CD_TRACETAB_DL4(string) +#define CD_TRACEDEC_DL4(value) +#define CD_TRACEHEX_DL4(value) +#define CD_TRACEBUF_DL4(pointer, len) +#define CD_WAIT_DL4(what) +#define CD_BREAKPOINT_DL4() + +#define CD_ASSERT_DL3(condition) +#define CD_POSTCODE_DL3(value) +#define CD_TRACE_DL3(string) +#define CD_TRACETAB_DL3(string) +#define CD_TRACEDEC_DL3(value) +#define CD_TRACEHEX_DL3(value) +#define CD_TRACEBUF_DL3(pointer, len) +#define CD_WAIT_DL3(what) +#define CD_BREAKPOINT_DL3() + +#define CD_ASSERT_DL2(condition) +#define CD_POSTCODE_DL2(value) +#define CD_TRACE_DL2(string) +#define CD_TRACETAB_DL2(string) +#define CD_TRACEDEC_DL2(value) +#define CD_TRACEHEX_DL2(value) +#define CD_TRACEBUF_DL2(pointer, len) +#define CD_WAIT_DL2(what) +#define CD_BREAKPOINT_DL2() + +#define CD_ASSERT_DL1(condition) +#define CD_POSTCODE_DL1(value) +#define CD_TRACE_DL1(string) +#define CD_TRACETAB_DL1(string) +#define CD_TRACEDEC_DL1(value) +#define CD_TRACEHEX_DL1(value) +#define CD_TRACEBUF_DL1(pointer, len) +#define CD_WAIT_DL1(what) +#define CD_BREAKPOINT_DL1() + + +#endif //#if (DEBUG_PARSER > 0) + + +#ifdef CHECKSTACK +VOID CD_fillstack(UINT16 size); +UINT16 CD_checkstack(UINT16 size); +#define CD_CHECKSTACK(stacksize) CD_checkstack(stacksize) +#define CD_FILLSTACK(stacksize) CD_fillstack(stacksize) +#else +#define CD_CHECKSTACK(stacksize) 0 +#define CD_FILLSTACK(stacksize) +#endif + + +#endif diff --git a/src/AtomBios/includes/Decoder.h b/src/AtomBios/includes/Decoder.h new file mode 100644 index 00000000..24c25fc2 --- /dev/null +++ b/src/AtomBios/includes/Decoder.h @@ -0,0 +1,86 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/*++ + +Module Name: + +Decoder.h + +Abstract: + +Includes all helper headers + +Revision History: + +NEG:27.08.2002 Initiated. +--*/ +#ifndef _DECODER_H_ +#define _DECODER_H_ +#define WS_QUOTIENT_C 64 +#define WS_REMINDER_C (WS_QUOTIENT_C+1) +#define WS_DATAPTR_C (WS_REMINDER_C+1) +#define WS_SHIFT_C (WS_DATAPTR_C+1) +#define WS_OR_MASK_C (WS_SHIFT_C+1) +#define WS_AND_MASK_C (WS_OR_MASK_C+1) +#define WS_FB_WINDOW_C (WS_AND_MASK_C+1) +#define WS_ATTRIBUTES_C (WS_FB_WINDOW_C+1) +#define PARSER_VERSION_MAJOR 0x00000000 +#define PARSER_VERSION_MINOR 0x0000000E +#define PARSER_VERSION (PARSER_VERSION_MAJOR | PARSER_VERSION_MINOR) +#include "CD_binding.h" +#include "CD_Common_Types.h" +#include "CD_hw_services.h" +#include "CD_Structs.h" +#include "CD_Definitions.h" +#include "CD_Opcodes.h" + +#define SOURCE_ONLY_CMD_TYPE 0//0xFE +#define SOURCE_DESTINATION_CMD_TYPE 1//0xFD +#define DESTINATION_ONLY_CMD_TYPE 2//0xFC + +#define ACCESS_TYPE_BYTE 0//0xF9 +#define ACCESS_TYPE_WORD 1//0xF8 +#define ACCESS_TYPE_DWORD 2//0xF7 +#define SWITCH_TYPE_ACCESS 3//0xF6 + +#define CD_CONTINUE 0//0xFB +#define CD_STOP 1//0xFA + + +#define IS_END_OF_TABLE(cmd) ((cmd) == EOT_OPCODE) +#define IS_COMMAND_VALID(cmd) (((cmd)<=LastValidCommand)&&((cmd)>=FirstValidCommand)) +#define IS_IT_SHIFT_COMMAND(Opcode) ((Opcode<=SHIFT_RIGHT_MC_OPCODE)&&(Opcode>=SHIFT_LEFT_REG_OPCODE)) +#define IS_IT_XXXX_COMMAND(Group, Opcode) ((Opcode<=Group##_MC_OPCODE)&&(Opcode>=Group##_REG_OPCODE)) +#define CheckCaseAndAdjustIP_Macro(size) \ + if (pParserTempData->SourceData32==(UINT32)((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.Value){\ + pParserTempData->CommandSpecific.ContinueSwitch = CD_STOP;\ + pParserTempData->pWorkingTableData->IP =(COMMAND_HEADER_POINTER *) RELATIVE_TO_TABLE(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.JumpOffset);\ + }else{\ + pParserTempData->pWorkingTableData->IP+=(sizeof (CASE_##size##ACCESS)\ + +sizeof(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->CaseSignature));\ + } + +#endif +/* pWorkingTableData->pCmd->Header.Attribute.SourceAlignment=alignmentLowerWord;\*/ + +// EOF diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h new file mode 100644 index 00000000..3eb5f776 --- /dev/null +++ b/src/AtomBios/includes/atombios.h @@ -0,0 +1,4306 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + + +/****************************************************************************/ +/*Portion I: Definitions shared between VBIOS and Driver */ +/****************************************************************************/ + + +#ifndef _ATOMBIOS_H +#define _ATOMBIOS_H + +#define ATOM_VERSION_MAJOR 0x00020000 +#define ATOM_VERSION_MINOR 0x00000002 + +#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) + + +#ifdef _H2INC + #ifndef ULONG + typedef unsigned long ULONG; + #endif + + #ifndef UCHAR + typedef unsigned char UCHAR; + #endif + + #ifndef USHORT + typedef unsigned short USHORT; + #endif +#endif + +#define ATOM_DAC_A 0 +#define ATOM_DAC_B 1 +#define ATOM_EXT_DAC 2 + +#define ATOM_CRTC1 0 +#define ATOM_CRTC2 1 + +#define ATOM_DIGA 0 +#define ATOM_DIGB 1 + +#define ATOM_PPLL1 0 +#define ATOM_PPLL2 1 + +#define ATOM_SCALER1 0 +#define ATOM_SCALER2 1 + +#define ATOM_SCALER_DISABLE 0 +#define ATOM_SCALER_CENTER 1 +#define ATOM_SCALER_EXPANSION 2 +#define ATOM_SCALER_MULTI_EX 3 + +#define ATOM_DISABLE 0 +#define ATOM_ENABLE 1 +#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) +#define ATOM_LCD_BLON (ATOM_ENABLE+2) +#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) +#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) +#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) +#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) + +#define ATOM_BLANKING 1 +#define ATOM_BLANKING_OFF 0 + +#define ATOM_CURSOR1 0 +#define ATOM_CURSOR2 1 + +#define ATOM_ICON1 0 +#define ATOM_ICON2 1 + +#define ATOM_CRT1 0 +#define ATOM_CRT2 1 + +#define ATOM_TV_NTSC 1 +#define ATOM_TV_NTSCJ 2 +#define ATOM_TV_PAL 3 +#define ATOM_TV_PALM 4 +#define ATOM_TV_PALCN 5 +#define ATOM_TV_PALN 6 +#define ATOM_TV_PAL60 7 +#define ATOM_TV_SECAM 8 +#define ATOM_TV_CV 16 + +#define ATOM_DAC1_PS2 1 +#define ATOM_DAC1_CV 2 +#define ATOM_DAC1_NTSC 3 +#define ATOM_DAC1_PAL 4 + +#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 +#define ATOM_DAC2_CV ATOM_DAC1_CV +#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC +#define ATOM_DAC2_PAL ATOM_DAC1_PAL + +#define ATOM_PM_ON 0 +#define ATOM_PM_STANDBY 1 +#define ATOM_PM_SUSPEND 2 +#define ATOM_PM_OFF 3 + +/* Bit0:{=0:single, =1:dual}, + Bit1 {=0:666RGB, =1:888RGB}, + Bit2:3:{Grey level} + Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ + +#define ATOM_PANEL_MISC_DUAL 0x00000001 +#define ATOM_PANEL_MISC_888RGB 0x00000002 +#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C +#define ATOM_PANEL_MISC_FPDI 0x00000010 +#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 +#define ATOM_PANEL_MISC_SPATIAL 0x00000020 +#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 +#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 + + +#define MEMTYPE_DDR1 "DDR1" +#define MEMTYPE_DDR2 "DDR2" +#define MEMTYPE_DDR3 "DDR3" +#define MEMTYPE_DDR4 "DDR4" + +#define ASIC_BUS_TYPE_PCI "PCI" +#define ASIC_BUS_TYPE_AGP "AGP" +#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" + +/* Maximum size of that FireGL flag string */ + +#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support +#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) + +#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop +#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING + +#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support +#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) + +#define HW_ASSISTED_I2C_STATUS_FAILURE 2 +#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 + +#pragma pack(1) /* BIOS data must use byte aligment */ + +/* Define offset to location of ROM header. */ + +#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L +#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L + +#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 +#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ +#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f +#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e + +/* Common header for all ROM Data tables. + Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. + And the pointer actually points to this header. */ + +typedef struct _ATOM_COMMON_TABLE_HEADER +{ + USHORT usStructureSize; + UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ + UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ + /*Image can't be updated, while Driver needs to carry the new table! */ +}ATOM_COMMON_TABLE_HEADER; + +typedef struct _ATOM_ROM_HEADER +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, + atombios should init it as "ATOM", don't change the position */ + USHORT usBiosRuntimeSegmentAddress; + USHORT usProtectedModeInfoOffset; + USHORT usConfigFilenameOffset; + USHORT usCRC_BlockOffset; + USHORT usBIOS_BootupMessageOffset; + USHORT usInt10Offset; + USHORT usPciBusDevInitCode; + USHORT usIoBaseAddress; + USHORT usSubsystemVendorID; + USHORT usSubsystemID; + USHORT usPCI_InfoOffset; + USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ + USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ + UCHAR ucExtendedFunctionCode; + UCHAR ucReserved; +}ATOM_ROM_HEADER; + +/*==============================Command Table Portion==================================== */ + +#ifdef UEFI_BUILD + #define UTEMP USHORT + #define USHORT void* +#endif + +typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ + USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 + USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON + USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT VRAM_BlockVenderDetection; + USHORT SetClocksRatio; + USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 + USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed + USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 + USHORT GPIOPinControl; //Atomic Table, only used by Bios + USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 + USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 + USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 + USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT MemoryPLLInit; + USHORT AdjustDisplayPll; //only used by Bios + USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios + USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios + USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 + USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 + USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT CV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetConditionalGoldenSetting; //only used by Bios + USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 + USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 + USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 + USHORT TV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableScaler; //Atomic Table, used only by Bios + USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 + USHORT EnableVGA_Access; //Obsolete , only used by Bios + USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 + USHORT SetCRTC_Replication; //Atomic Table, used only by Bios + USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios + USHORT UpdateCRTC_DoubleBufferRegisters; + USHORT LUT_AutoFill; //Atomic Table, only used by Bios + USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios + USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 + USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT VRAM_BlockDetectionByStrap; + USHORT MemoryCleanUp; //Atomic Table, only used by Bios + USHORT ReadEDIDFromHWAssistedI2C; //Function Table,only used by Bios + USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components + USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components + USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init + USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock + USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock + USHORT VRAM_GetCurrentInfoBlock; + USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT MemoryTraining; + USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 + USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 + USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" + USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init + USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender + USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios + USHORT DPEncoderService; //Function Table,only used by Bios +}ATOM_MASTER_LIST_OF_COMMAND_TABLES; + +#define UNIPHYTransmitterControl DIG1TransmitterControl +#define LVTMATransmitterControl DIG2TransmitterControl +#define SetCRTC_DPM_State GetConditionalGoldenSetting + +typedef struct _ATOM_MASTER_COMMAND_TABLE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; +}ATOM_MASTER_COMMAND_TABLE; + +typedef struct _ATOM_TABLE_ATTRIBUTE +{ + USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), + USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag +}ATOM_TABLE_ATTRIBUTE; + +// Common header for all command tables. +//Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. +//And the pointer actually points to this header. + +typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER +{ + ATOM_COMMON_TABLE_HEADER CommonHeader; + ATOM_TABLE_ATTRIBUTE TableAttribute; +}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; + + +typedef struct _ASIC_INIT_PARAMETERS +{ + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit +}ASIC_INIT_PARAMETERS; + +#define COMPUTE_MEMORY_PLL_PARAM 1 +#define COMPUTE_ENGINE_PLL_PARAM 2 + +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS +{ + ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div + UCHAR ucAction; //0:reserved //1:Memory //2:Engine + UCHAR ucReserved; //may expand to return larger Fbdiv later + UCHAR ucFbDiv; //return value + UCHAR ucPostDiv; //return value +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; + +typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 +{ + ULONG ulClock; //When return, [23:0] return real clock + UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register + USHORT usFbDiv; //return Feedback value to be written to register + UCHAR ucPostDiv; //return post div to be written to register +}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; +#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS + + +#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value +#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) +#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition +#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change +#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup +#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL +#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK + +#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) +#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition +#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change +#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup +#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL + +typedef struct _SET_ENGINE_CLOCK_PARAMETERS +{ + ULONG ulTargetEngineClock; //In 10Khz unit +}SET_ENGINE_CLOCK_PARAMETERS; + +typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION +{ + ULONG ulTargetEngineClock; //In 10Khz unit + COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; +}SET_ENGINE_CLOCK_PS_ALLOCATION; + + +typedef struct _SET_MEMORY_CLOCK_PARAMETERS +{ + ULONG ulTargetMemoryClock; //In 10Khz unit +}SET_MEMORY_CLOCK_PARAMETERS; + +typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION +{ + ULONG ulTargetMemoryClock; //In 10Khz unit + COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; +}SET_MEMORY_CLOCK_PS_ALLOCATION; + +typedef struct _ASIC_INIT_PS_ALLOCATION +{ + ASIC_INIT_PARAMETERS sASICInitClocks; + SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure +}ASIC_INIT_PS_ALLOCATION; + + +typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[3]; +}DYNAMIC_CLOCK_GATING_PARAMETERS; +#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS + + +typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[3]; +}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; +#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS + + +typedef struct _DAC_LOAD_DETECTION_PARAMETERS +{ + USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} + UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} + UCHAR ucMisc; //Valid only when table revision =1.3 and above +}DAC_LOAD_DETECTION_PARAMETERS; + +// DAC_LOAD_DETECTION_PARAMETERS.ucMisc +#define DAC_LOAD_MISC_YPrPb 0x01 + + +typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION +{ + DAC_LOAD_DETECTION_PARAMETERS sDacload; + ULONG Reserved[2];// Don't set this one, allocation for EXT DAC +}DAC_LOAD_DETECTION_PS_ALLOCATION; + + +typedef struct _DAC_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx + // 1: PS2 + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder +}DAC_ENCODER_CONTROL_PARAMETERS; + +#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS + +typedef struct _TV_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder +}TV_ENCODER_CONTROL_PARAMETERS; + +typedef struct _DIG_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucConfig; + // [2] Link Select: + // =0: PHY linkA if bfLane<3 + // =1: PHY linkB if bfLanes<3 + // =0: PHY linkA+B if bfLanes=3 + // [3] Transmitter Sel + // =0: UNIPHY or PCIEPHY + // =1: LVTMA + UCHAR ucAction; // =0: turn off encoder + // =1: turn on encoder + union{ + UCHAR ucEncoderMode; + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder + // =3: HDMI encoder + // =4: SDVO encoder + UCHAR ucEncoderType; + }; + UCHAR ucLaneNum; // how many lanes to enable + UCHAR ucReserved[2]; +}DIG_ENCODER_CONTROL_PARAMETERS; +#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS +#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS +#define EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PS_ALLOCATION + +//ucConfig +#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 +#define ATOM_ENCODER_CONFIG_LINKA 0x00 +#define ATOM_ENCODER_CONFIG_LINKB 0x04 +#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA +#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 +#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 +#define ATOM_ENCODER_CONFIG_LVTMA 0x08 +#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 +#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 +#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 +// ucAction +// ATOM_ENABLE: Enable Encoder +// ATOM_DISABLE: Disable Encoder + +//ucEncoderMode +#define ATOM_ENCODER_MODE_DP 0 +#define ATOM_ENCODER_MODE_LVDS 1 +#define ATOM_ENCODER_MODE_DVI 2 +#define ATOM_ENCODER_MODE_HDMI 3 +#define ATOM_ENCODER_MODE_SDVO 4 +#define ATOM_ENCODER_MODE_TV 13 +#define ATOM_ENCODER_MODE_CV 14 +#define ATOM_ENCODER_MODE_CRT 15 + +typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS +{ + union + { + USHORT usPixelClock; // in 10KHz; for bios convenient + USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h + }; + UCHAR ucConfig; + // [0]=0: 4 lane Link, + // =1: 8 lane Link ( Dual Links TMDS ) + // [1]=0: InCoherent mode + // =1: Coherent Mode + // [2] Link Select: + // =0: PHY linkA if bfLane<3 + // =1: PHY linkB if bfLanes<3 + // =0: PHY linkA+B if bfLanes=3 + // [5:4]PCIE lane Sel + // =0: lane 0~3 or 0~7 + // =1: lane 4~7 + // =2: lane 8~11 or 8~15 + // =3: lane 12~15 + UCHAR ucAction; // =0: turn off encoder + // =1: turn on encoder + UCHAR ucReserved[4]; +}DIG_TRANSMITTER_CONTROL_PARAMETERS; + +#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS + +//ucInitInfo +#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff + +//ucConfig +#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 +#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 +#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 +#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 +#define ATOM_TRANSMITTER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 +#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 +#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 +#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 +#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 +#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 +#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 +#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 +#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 + +//ucAction +#define ATOM_TRANSMITTER_ACTION_DISABLE 0 +#define ATOM_TRANSMITTER_ACTION_ENABLE 1 +#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 +#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 +#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 +#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 +#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 +#define ATOM_TRANSMITTER_ACTION_INIT 7 +#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 8 +#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 9 +#define ATOM_TRANSMITTER_ACTION_SETUP 10 + + +/****************************Device Output Control Command Table Definitions**********************/ +typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +{ + UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE + // When the display is LCD, in addition to above: + // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| + // ATOM_LCD_SELFTEST_STOP + + UCHAR aucPadding[3]; // padding to DWORD aligned +}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; + +#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS + + +#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION +#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS + +/**************************************************************************/ +typedef struct _BLANK_CRTC_PARAMETERS +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF + USHORT usBlackColorRCr; + USHORT usBlackColorGY; + USHORT usBlackColorBCb; +}BLANK_CRTC_PARAMETERS; +#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS + + +typedef struct _ENABLE_CRTC_PARAMETERS +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[2]; +}ENABLE_CRTC_PARAMETERS; +#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS + + +typedef struct _SET_CRTC_OVERSCAN_PARAMETERS +{ + USHORT usOverscanRight; // right + USHORT usOverscanLeft; // left + USHORT usOverscanBottom; // bottom + USHORT usOverscanTop; // top + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucPadding[3]; +}SET_CRTC_OVERSCAN_PARAMETERS; +#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS + + +typedef struct _SET_CRTC_REPLICATION_PARAMETERS +{ + UCHAR ucH_Replication; // horizontal replication + UCHAR ucV_Replication; // vertical replication + UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucPadding; +}SET_CRTC_REPLICATION_PARAMETERS; +#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS + + +typedef struct _SELECT_CRTC_SOURCE_PARAMETERS +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... + UCHAR ucPadding[2]; +}SELECT_CRTC_SOURCE_PARAMETERS; +#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS + +typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 +{ + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO + UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO + UCHAR ucPadding; +}SELECT_CRTC_SOURCE_PARAMETERS_V2; + +//ucEncoderID +//#define ASIC_INT_DAC1_ENCODER_ID 0x00 +//#define ASIC_INT_TV_ENCODER_ID 0x02 +//#define ASIC_INT_DIG1_ENCODER_ID 0x03 +//#define ASIC_INT_DAC2_ENCODER_ID 0x04 +//#define ASIC_EXT_TV_ENCODER_ID 0x06 +//#define ASIC_INT_DVO_ENCODER_ID 0x07 +//#define ASIC_INT_DIG2_ENCODER_ID 0x09 +//#define ASIC_EXT_DIG_ENCODER_ID 0x05 + +//ucEncodeMode +//#define ATOM_ENCODER_MODE_DP 0 +//#define ATOM_ENCODER_MODE_LVDS 1 +//#define ATOM_ENCODER_MODE_DVI 2 +//#define ATOM_ENCODER_MODE_HDMI 3 +//#define ATOM_ENCODER_MODE_SDVO 4 +//#define ATOM_ENCODER_MODE_TV 13 +//#define ATOM_ENCODER_MODE_CV 14 +//#define ATOM_ENCODER_MODE_CRT 15 + +//Major revision=1., Minor revision=1 +typedef struct _PIXEL_CLOCK_PARAMETERS +{ + USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) + // 0 means disable PPLL + USHORT usRefDiv; // Reference divider + USHORT usFbDiv; // feedback divider + UCHAR ucPostDiv; // post divider + UCHAR ucFracFbDiv; // fractional feedback divider + UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 + UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER + UCHAR ucCRTC; // Which CRTC uses this Ppll + UCHAR ucPadding; +}PIXEL_CLOCK_PARAMETERS; + + +//Major revision=1., Minor revision=2, add ucMiscIfno +//ucMiscInfo: +#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 +#define MISC_DEVICE_INDEX_MASK 0xF0 +#define MISC_DEVICE_INDEX_SHIFT 4 + +typedef struct _PIXEL_CLOCK_PARAMETERS_V2 +{ + USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) + // 0 means disable PPLL + USHORT usRefDiv; // Reference divider + USHORT usFbDiv; // feedback divider + UCHAR ucPostDiv; // post divider + UCHAR ucFracFbDiv; // fractional feedback divider + UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 + UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER + UCHAR ucCRTC; // Which CRTC uses this Ppll + UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog +}PIXEL_CLOCK_PARAMETERS_V2; + +//Major revision=1., Minor revision=3, structure/definition change +//ucEncoderMode: +//ATOM_ENCODER_MODE_DP +//ATOM_ENOCDER_MODE_LVDS +//ATOM_ENOCDER_MODE_DVI +//ATOM_ENOCDER_MODE_HDMI +//ATOM_ENOCDER_MODE_SDVO +//ATOM_ENCODER_MODE_TV 13 +//ATOM_ENCODER_MODE_CV 14 +//ATOM_ENCODER_MODE_CRT 15 + +//ucMiscInfo: also changed, see below +#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 +#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 +#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 +#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 +#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 + +typedef struct _PIXEL_CLOCK_PARAMETERS_V3 +{ + USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) + // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. + USHORT usRefDiv; // Reference divider + USHORT usFbDiv; // feedback divider + UCHAR ucPostDiv; // post divider + UCHAR ucFracFbDiv; // fractional feedback divider + UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 + UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h + UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ + UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel +}PIXEL_CLOCK_PARAMETERS_V3; + +#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 +#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST + +typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS +{ + USHORT usPixelClock; + UCHAR ucTransmitterID; + UCHAR ucEncodeMode; + union + { + UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit + UCHAR ucConfig; //if none DVO, not defined yet + }; + UCHAR ucReserved[3]; +}ADJUST_DISPLAY_PLL_PARAMETERS; + +#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS + +typedef struct _ENABLE_YUV_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) + UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format + UCHAR ucPadding[2]; +}ENABLE_YUV_PARAMETERS; +#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS + +typedef struct _GET_MEMORY_CLOCK_PARAMETERS +{ + ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit +} GET_MEMORY_CLOCK_PARAMETERS; +#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS + + +typedef struct _GET_ENGINE_CLOCK_PARAMETERS +{ + ULONG ulReturnEngineClock; // current engine speed in 10KHz unit +} GET_ENGINE_CLOCK_PARAMETERS; +#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS + + +//Maxium 8 bytes,the data read in will be placed in the parameter space. +//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed +typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS +{ + USHORT usPrescale; //Ratio between Engine clock and I2C clock + USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID + USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status + //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte + UCHAR ucSlaveAddr; //Read from which slave + UCHAR ucLineNumber; //Read from which HW assisted line +}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; +#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS + + +#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 +#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 +#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 +#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 +#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 + +typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS +{ + USHORT usPrescale; //Ratio between Engine clock and I2C clock + USHORT usByteOffset; //Write to which byte + //Upper portion of usByteOffset is Format of data + //1bytePS+offsetPS + //2bytesPS+offsetPS + //blockID+offsetPS + //blockID+offsetID + //blockID+counterID+offsetID + UCHAR ucData; //PS data1 + UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 + UCHAR ucSlaveAddr; //Write to which slave + UCHAR ucLineNumber; //Write from which HW assisted line +}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; + +#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS + +typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS +{ + USHORT usPrescale; //Ratio between Engine clock and I2C clock + UCHAR ucSlaveAddr; //Write to which slave + UCHAR ucLineNumber; //Write from which HW assisted line +}SET_UP_HW_I2C_DATA_PARAMETERS; + + +/**************************************************************************/ +#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS + +typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS +{ + UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected + UCHAR ucPwrBehaviorId; + USHORT usPwrBudget; //how much power currently boot to in unit of watt +}POWER_CONNECTOR_DETECTION_PARAMETERS; + +typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION +{ + UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected + UCHAR ucReserved; + USHORT usPwrBudget; //how much power currently boot to in unit of watt + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; + +/****************************LVDS SS Command Table Definitions**********************/ +typedef struct _ENABLE_LVDS_SS_PARAMETERS +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD + UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY + UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE + UCHAR ucPadding[3]; +}ENABLE_LVDS_SS_PARAMETERS; + +//ucTableFormatRevision=1,ucTableContentRevision=2 +typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD + UCHAR ucSpreadSpectrumStep; // + UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE + UCHAR ucSpreadSpectrumDelay; + UCHAR ucSpreadSpectrumRange; + UCHAR ucPadding; +}ENABLE_LVDS_SS_PARAMETERS_V2; + +//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. +typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD + UCHAR ucSpreadSpectrumStep; // + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucSpreadSpectrumDelay; + UCHAR ucSpreadSpectrumRange; + UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 +}ENABLE_SPREAD_SPECTRUM_ON_PPLL; + +#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL + +/**************************************************************************/ + +typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION +{ + PIXEL_CLOCK_PARAMETERS sPCLKInput; + ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion +}SET_PIXEL_CLOCK_PS_ALLOCATION; + +#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION + +typedef struct _MEMORY_TRAINING_PARAMETERS +{ + ULONG ulTargetMemoryClock; //In 10Khz unit +}MEMORY_TRAINING_PARAMETERS; +#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS + + + +/****************************LVDS and other encoder command table definitions **********************/ +typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucMisc; // bit0=0: Enable single link + // =1: Enable dual link + // Bit1=0: 666RGB + // =1: 888RGB + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder +}LVDS_ENCODER_CONTROL_PARAMETERS; + +#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS + +#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS +#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS + +#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS +#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS + +typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS +{ + UCHAR ucEnable; // Enable or Disable External TMDS encoder + UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} + UCHAR ucPadding[2]; +}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; + +typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION +{ + ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion +}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; + + +//ucTableFormatRevision=1,ucTableContentRevision=2 +typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 +{ + USHORT usPixelClock; // in 10KHz; for bios convenient + UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below + UCHAR ucAction; // 0: turn off encoder + // 1: setup and turn on encoder + UCHAR ucTruncate; // bit0=0: Disable truncate + // =1: Enable truncate + // bit4=0: 666RGB + // =1: 888RGB + UCHAR ucSpatial; // bit0=0: Disable spatial dithering + // =1: Enable spatial dithering + // bit4=0: 666RGB + // =1: 888RGB + UCHAR ucTemporal; // bit0=0: Disable temporal dithering + // =1: Enable temporal dithering + // bit4=0: 666RGB + // =1: 888RGB + // bit5=0: Gray level 2 + // =1: Gray level 4 + UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E + // =1: 25FRC_SEL pattern F + // bit6:5=0: 50FRC_SEL pattern A + // =1: 50FRC_SEL pattern B + // =2: 50FRC_SEL pattern C + // =3: 50FRC_SEL pattern D + // bit7=0: 75FRC_SEL pattern E + // =1: 75FRC_SEL pattern F +}LVDS_ENCODER_CONTROL_PARAMETERS_V2; + +#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 + +#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 +#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 + +#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 +#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 +#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 + +typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 +{ + ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion +}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; + + +//ucTableFormatRevision=1,ucTableContentRevision=3 + +//ucDVOConfig: +#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 +#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 +#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 +#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c +#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 +#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 +#define DVO_ENCODER_CONFIG_24BIT 0x08 + +typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 +{ + USHORT usPixelClock; + UCHAR ucDVOConfig; + UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT + UCHAR ucReseved[4]; +}DVO_ENCODER_CONTROL_PARAMETERS_V3; +#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 + +//ucTableFormatRevision=1 +//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for +// bit1=0: non-coherent mode +// =1: coherent mode + +#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 +#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 + +#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 + +#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 + +//========================================================================================== +//Only change is here next time when changing encoder parameter definitions again! +#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST + +#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST + +#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 +#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST + +#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS +#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION + +//========================================================================================== +#define PANEL_ENCODER_MISC_DUAL 0x01 +#define PANEL_ENCODER_MISC_COHERENT 0x02 +#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 +#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 + +#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE +#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE +#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) + +#define PANEL_ENCODER_TRUNCATE_EN 0x01 +#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 +#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 +#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 +#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 +#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 +#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 +#define PANEL_ENCODER_25FRC_MASK 0x10 +#define PANEL_ENCODER_25FRC_E 0x00 +#define PANEL_ENCODER_25FRC_F 0x10 +#define PANEL_ENCODER_50FRC_MASK 0x60 +#define PANEL_ENCODER_50FRC_A 0x00 +#define PANEL_ENCODER_50FRC_B 0x20 +#define PANEL_ENCODER_50FRC_C 0x40 +#define PANEL_ENCODER_50FRC_D 0x60 +#define PANEL_ENCODER_75FRC_MASK 0x80 +#define PANEL_ENCODER_75FRC_E 0x00 +#define PANEL_ENCODER_75FRC_F 0x80 + +/**************************************************************************/ + +#define SET_VOLTAGE_TYPE_ASIC_VDDC 1 +#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 +#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 +#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 + +#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 +#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 +#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 + +#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 +#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 +#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 + +typedef struct _SET_VOLTAGE_PARAMETERS +{ + UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ + UCHAR ucVoltageMode; // To set all, to set source A or source B or ... + UCHAR ucVoltageIndex; // An index to tell which voltage level + UCHAR ucReserved; +}SET_VOLTAGE_PARAMETERS; + + +typedef struct _SET_VOLTAGE_PARAMETERS_V2 +{ + UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ + UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode + USHORT usVoltageLevel; // real voltage level +}SET_VOLTAGE_PARAMETERS_V2; + + +typedef struct _SET_VOLTAGE_PS_ALLOCATION +{ + SET_VOLTAGE_PARAMETERS sASICSetVoltage; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +}SET_VOLTAGE_PS_ALLOCATION; + +typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION +{ + TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one +}TV_ENCODER_CONTROL_PS_ALLOCATION; + +//==============================Data Table Portion==================================== + +#ifdef UEFI_BUILD + #define UTEMP USHORT + #define USHORT void* +#endif + +typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES +{ + USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! + USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios + USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios + USHORT StandardVESA_Timing; // Only used by Bios + USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 + USHORT DAC_Info; // Will be obsolete from R600 + USHORT LVDS_Info; // Shared by various SW components,latest version 1.1 + USHORT TMDS_Info; // Will be obsolete from R600 + USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 + USHORT SupportedDevicesInfo; // Will be obsolete from R600 + USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 + USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 + USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 + USHORT VESA_ToInternalModeLUT; // Only used by Bios + USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 + USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 + USHORT CompassionateData; // Will be obsolete from R600 + USHORT SaveRestoreInfo; // Only used by Bios + USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info + USHORT OemInfo; // Defined and used by external SW, should be obsolete soon + USHORT XTMDS_Info; // Will be obsolete from R600 + USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used + USHORT Object_Header; // Shared by various SW components,latest version 1.1 + USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! + USHORT MC_InitParameter; // Only used by command table + USHORT ASIC_VDDC_Info; // Will be obsolete from R600 + USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" + USHORT TV_VideoMode; // Only used by command table + USHORT VRAM_Info; // Only used by command table, latest version 1.3 + USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 + USHORT IntegratedSystemInfo; // Shared by various SW components + USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 + USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 + USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 +}ATOM_MASTER_LIST_OF_DATA_TABLES; + +#ifdef UEFI_BUILD + #define USHORT UTEMP +#endif + + +typedef struct _ATOM_MASTER_DATA_TABLE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; +}ATOM_MASTER_DATA_TABLE; + + +typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulSignature; // HW info table signature string "$ATI" + UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) + UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) + UCHAR ucVideoPortInfo; // Provides the video port capabilities + UCHAR ucHostPortInfo; // Provides host port configuration information +}ATOM_MULTIMEDIA_CAPABILITY_INFO; + + +typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulSignature; // MM info table signature sting "$MMT" + UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) + UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) + UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting + UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) + UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) + UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) + UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) + UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) + UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) +}ATOM_MULTIMEDIA_CONFIG_INFO; + +/****************************Firmware Info Table Definitions**********************/ + +// usBIOSCapability Defintion: +// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; +// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; +// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; +// Others: Reserved +#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 +#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 +#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 +#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 +#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 +#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 +#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 +#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 +#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 +#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 +#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 +#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 + + +#ifndef _H2INC + +//Please don't add or expand this bitfield structure below, this one will retire soon.! +typedef struct _ATOM_FIRMWARE_CAPABILITY +{ + USHORT FirmwarePosted:1; + USHORT DualCRTC_Support:1; + USHORT ExtendedDesktopSupport:1; + USHORT MemoryClockSS_Support:1; + USHORT EngineClockSS_Support:1; + USHORT GPUControlsBL:1; + USHORT WMI_SUPPORT:1; + USHORT PPMode_Assigned:1; + USHORT HyperMemory_Support:1; + USHORT HyperMemory_Size:4; + USHORT Reserved:3; +}ATOM_FIRMWARE_CAPABILITY; + +typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS +{ + ATOM_FIRMWARE_CAPABILITY sbfAccess; + USHORT susAccess; +}ATOM_FIRMWARE_CAPABILITY_ACCESS; + +#else + +typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS +{ + USHORT susAccess; +}ATOM_FIRMWARE_CAPABILITY_ACCESS; + +#endif + +typedef struct _ATOM_FIRMWARE_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucPadding[3]; //Don't use them + ULONG aulReservedForBIOS[3]; //Don't use them + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO; + +typedef struct _ATOM_FIRMWARE_INFO_V1_2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + UCHAR ucPadding[2]; //Don't use them + ULONG aulReservedForBIOS[2]; //Don't use them + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO_V1_2; + +typedef struct _ATOM_FIRMWARE_INFO_V1_3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + UCHAR ucPadding[2]; //Don't use them + ULONG aulReservedForBIOS; //Don't use them + ULONG ul3DAccelerationEngineClock;//In 10Khz unit + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO_V1_3; + +typedef struct _ATOM_FIRMWARE_INFO_V1_4 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulFirmwareRevision; + ULONG ulDefaultEngineClock; //In 10Khz unit + ULONG ulDefaultMemoryClock; //In 10Khz unit + ULONG ulDriverTargetEngineClock; //In 10Khz unit + ULONG ulDriverTargetMemoryClock; //In 10Khz unit + ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit + ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit + ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit + ULONG ulASICMaxEngineClock; //In 10Khz unit + ULONG ulASICMaxMemoryClock; //In 10Khz unit + UCHAR ucASICMaxTemperature; + UCHAR ucMinAllowedBL_Level; + USHORT usBootUpVDDCVoltage; //In MV unit + USHORT usLcdMinPixelClockPLL_Output; // In MHz unit + USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit + ULONG ul3DAccelerationEngineClock;//In 10Khz unit + ULONG ulMinPixelClockPLL_Output; //In 10Khz unit + USHORT usMinEngineClockPLL_Input; //In 10Khz unit + USHORT usMaxEngineClockPLL_Input; //In 10Khz unit + USHORT usMinEngineClockPLL_Output; //In 10Khz unit + USHORT usMinMemoryClockPLL_Input; //In 10Khz unit + USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit + USHORT usMinMemoryClockPLL_Output; //In 10Khz unit + USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk + USHORT usMinPixelClockPLL_Input; //In 10Khz unit + USHORT usMaxPixelClockPLL_Input; //In 10Khz unit + USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output + ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit + UCHAR ucDesign_ID; //Indicate what is the board design + UCHAR ucMemoryModule_ID; //Indicate what is the board design +}ATOM_FIRMWARE_INFO_V1_4; + +#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V1_4 + +#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 +#define IGP_CAP_FLAG_AC_CARD 0x4 +#define IGP_CAP_FLAG_SDVO_CARD 0x8 +#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 + +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; //in 10kHz unit + ULONG ulBootUpMemoryClock; //in 10kHz unit + ULONG ulMaxSystemMemoryClock; //in 10kHz unit + ULONG ulMinSystemMemoryClock; //in 10kHz unit + UCHAR ucNumberOfCyclesInPeriodHi; + UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. + USHORT usReserved1; + USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage + USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage + ULONG ulReserved[2]; + + USHORT usFSBClock; //In MHz unit + USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable + //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card + //Bit[4]==1: P/2 mode, ==0: P/1 mode + USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal + USHORT usK8MemoryClock; //in MHz unit + USHORT usK8SyncStartDelay; //in 0.01 us unit + USHORT usK8DataReturnTime; //in 0.01 us unit + UCHAR ucMaxNBVoltage; + UCHAR ucMinNBVoltage; + UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved + UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod + UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime + UCHAR ucHTLinkWidth; //16 bit vs. 8 bit + UCHAR ucMaxNBVoltageHigh; + UCHAR ucMinNBVoltageHigh; +}ATOM_INTEGRATED_SYSTEM_INFO; + +/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO +ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock + For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock +ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 + For AMD IGP,for now this can be 0 +ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 + For AMD IGP,for now this can be 0 + +usFSBClock: For Intel IGP,it's FSB Freq + For AMD IGP,it's HT Link Speed + +usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 +usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation +usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation + +VC:Voltage Control +ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. +ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. + +ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. +ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 + +ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. +ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. + + +usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. +usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. +*/ + + +/* +The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; +Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. +The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. + +SW components can access the IGP system infor structure in the same way as before +*/ + + +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ULONG ulBootUpEngineClock; //in 10kHz unit + ULONG ulReserved1[2]; //must be 0x0 for the reserved + ULONG ulBootUpUMAClock; //in 10kHz unit + ULONG ulBootUpSidePortClock; //in 10kHz unit + ULONG ulReserved2[8]; //must be 0x0 for the reserved + ULONG ulBootUpReqDisplayVector; + ULONG ulOtherDisplayMisc; + ULONG ulDDISlot1Config; + ULONG ulDDISlot2Config; + UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved + UCHAR ucReserved; //must be 0x0 for the reserved + UCHAR ucDockingPinBit; + UCHAR ucDockingPinPolarity; + ULONG ulDockingPinCFGInfo; + ULONG ulCPUCapInfo; + ULONG ulReserved3[107]; //must be 0x0 +}ATOM_INTEGRATED_SYSTEM_INFO_V2; + +/* +ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; +ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present +ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present + + +ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. + +ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; + [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; + +ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). + [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) + [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) + [15:8] - Lane configuration attribute; + [31:16]- Reserved + +ulDDISlot2Config: Same as Slot1 + +ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin +ucDockingPinBit: which bit in this register to read the pin status; +ucDockingPinPolarity:Polarity of the pin when docked; + +ulCPUCapInfo: TBD + +*/ + +#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 +#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 +#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 +#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 +#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 +#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 +#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 +#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 +#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 +#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 +#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A +#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B +#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C +#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D + +// define ASIC internal encoder id ( bit vector ) +#define ASIC_INT_DAC1_ENCODER_ID 0x00 +#define ASIC_INT_TV_ENCODER_ID 0x02 +#define ASIC_INT_DIG1_ENCODER_ID 0x03 +#define ASIC_INT_DAC2_ENCODER_ID 0x04 +#define ASIC_EXT_TV_ENCODER_ID 0x06 +#define ASIC_INT_DVO_ENCODER_ID 0x07 +#define ASIC_INT_DIG2_ENCODER_ID 0x09 +#define ASIC_EXT_DIG_ENCODER_ID 0x05 + +//define Encoder attribute +#define ATOM_ANALOG_ENCODER 0 +#define ATOM_DIGITAL_ENCODER 1 + +#define ATOM_DEVICE_CRT1_INDEX 0x00000000 +#define ATOM_DEVICE_LCD1_INDEX 0x00000001 +#define ATOM_DEVICE_TV1_INDEX 0x00000002 +#define ATOM_DEVICE_DFP1_INDEX 0x00000003 +#define ATOM_DEVICE_CRT2_INDEX 0x00000004 +#define ATOM_DEVICE_LCD2_INDEX 0x00000005 +#define ATOM_DEVICE_TV2_INDEX 0x00000006 +#define ATOM_DEVICE_DFP2_INDEX 0x00000007 +#define ATOM_DEVICE_CV_INDEX 0x00000008 +#define ATOM_DEVICE_DFP3_INDEX 0x00000009 +#define ATOM_DEVICE_RESERVEDA_INDEX 0x0000000A +#define ATOM_DEVICE_RESERVEDB_INDEX 0x0000000B +#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C +#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D +#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E +#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F +#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_CV_INDEX+2) +#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO +#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) + +#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) +#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) +#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) +#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX) +#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) +#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) +#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX ) +#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX) +#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) +#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) + +#define ATOM_DEVICE_CRT_SUPPORT ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT +#define ATOM_DEVICE_DFP_SUPPORT ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT +#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT | ATOM_DEVICE_TV2_SUPPORT +#define ATOM_DEVICE_LCD_SUPPORT ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT + +#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 +#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 +#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 +#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 +#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 +#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 +#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 +#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 +#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 +#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 +#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 +#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A +#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B +#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E +#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F + + +#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F +#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 +#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 +#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 +#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 +#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 + +#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 + +#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F +#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 + +#define ATOM_DEVICE_I2C_ID_MASK 0x00000070 +#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 +#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 +#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 +#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 +#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 + +#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 +#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 +#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 +#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 + +// usDeviceSupport: +// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported +// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported +// Bit 2 = 0 - no TV1 support= 1- TV1 is supported +// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported +// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported +// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported +// Bit 6 = 0 - no TV2 support= 1- TV2 is supported +// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported +// Bit 8 = 0 - no CV support= 1- CV is supported +// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported +// Byte1 (Supported Device Info) +// Bit 0 = = 0 - no CV support= 1- CV is supported +// +// + +// ucI2C_ConfigID +// [7:0] - I2C LINE Associate ID +// = 0 - no I2C +// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) +// = 0, [6:0]=SW assisted I2C ID +// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use +// = 2, HW engine for Multimedia use +// = 3-7 Reserved for future I2C engines +// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C + + +typedef struct _ATOM_I2C_ID_CONFIG +{ + UCHAR bfI2C_LineMux:4; + UCHAR bfHW_EngineID:3; + UCHAR bfHW_Capable:1; +}ATOM_I2C_ID_CONFIG; + +typedef union _ATOM_I2C_ID_CONFIG_ACCESS +{ + ATOM_I2C_ID_CONFIG sbfAccess; + UCHAR ucAccess; +}ATOM_I2C_ID_CONFIG_ACCESS; + + +typedef struct _ATOM_GPIO_I2C_ASSIGMENT +{ + USHORT usClkMaskRegisterIndex; + USHORT usClkEnRegisterIndex; + USHORT usClkY_RegisterIndex; + USHORT usClkA_RegisterIndex; + USHORT usDataMaskRegisterIndex; + USHORT usDataEnRegisterIndex; + USHORT usDataY_RegisterIndex; + USHORT usDataA_RegisterIndex; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; + UCHAR ucClkMaskShift; + UCHAR ucClkEnShift; + UCHAR ucClkY_Shift; + UCHAR ucClkA_Shift; + UCHAR ucDataMaskShift; + UCHAR ucDataEnShift; + UCHAR ucDataY_Shift; + UCHAR ucDataA_Shift; + UCHAR ucReserved1; + UCHAR ucReserved2; +}ATOM_GPIO_I2C_ASSIGMENT; + +typedef struct _ATOM_GPIO_I2C_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; +}ATOM_GPIO_I2C_INFO; + + +#ifndef _H2INC + +//Please don't add or expand this bitfield structure below, this one will retire soon.! +typedef struct _ATOM_MODE_MISC_INFO +{ + USHORT HorizontalCutOff:1; + USHORT HSyncPolarity:1; //0=Active High, 1=Active Low + USHORT VSyncPolarity:1; //0=Active High, 1=Active Low + USHORT VerticalCutOff:1; + USHORT H_ReplicationBy2:1; + USHORT V_ReplicationBy2:1; + USHORT CompositeSync:1; + USHORT Interlace:1; + USHORT DoubleClock:1; + USHORT RGB888:1; + USHORT Reserved:6; +}ATOM_MODE_MISC_INFO; + +typedef union _ATOM_MODE_MISC_INFO_ACCESS +{ + ATOM_MODE_MISC_INFO sbfAccess; + USHORT usAccess; +}ATOM_MODE_MISC_INFO_ACCESS; + +#else + +typedef union _ATOM_MODE_MISC_INFO_ACCESS +{ + USHORT usAccess; +}ATOM_MODE_MISC_INFO_ACCESS; + +#endif + +// usModeMiscInfo- +#define ATOM_H_CUTOFF 0x01 +#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low +#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low +#define ATOM_V_CUTOFF 0x08 +#define ATOM_H_REPLICATIONBY2 0x10 +#define ATOM_V_REPLICATIONBY2 0x20 +#define ATOM_COMPOSITESYNC 0x40 +#define ATOM_INTERLACE 0x80 +#define ATOM_DOUBLE_CLOCK_MODE 0x100 +#define ATOM_RGB888_MODE 0x200 + +//usRefreshRate- +#define ATOM_REFRESH_43 43 +#define ATOM_REFRESH_47 47 +#define ATOM_REFRESH_56 56 +#define ATOM_REFRESH_60 60 +#define ATOM_REFRESH_65 65 +#define ATOM_REFRESH_70 70 +#define ATOM_REFRESH_72 72 +#define ATOM_REFRESH_75 75 +#define ATOM_REFRESH_85 85 + +// ATOM_MODE_TIMING data are exactly the same as VESA timing data. +// Translation from EDID to ATOM_MODE_TIMING, use the following formula. +// +// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK +// = EDID_HA + EDID_HBL +// VESA_HDISP = VESA_ACTIVE = EDID_HA +// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH +// = EDID_HA + EDID_HSO +// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW +// VESA_BORDER = EDID_BORDER + + +typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS +{ + USHORT usH_Size; + USHORT usH_Blanking_Time; + USHORT usV_Size; + USHORT usV_Blanking_Time; + USHORT usH_SyncOffset; + USHORT usH_SyncWidth; + USHORT usV_SyncOffset; + USHORT usV_SyncWidth; + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + UCHAR ucH_Border; // From DFP EDID + UCHAR ucV_Border; + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucPadding[3]; +}SET_CRTC_USING_DTD_TIMING_PARAMETERS; + +typedef struct _SET_CRTC_TIMING_PARAMETERS +{ + USHORT usH_Total; // horizontal total + USHORT usH_Disp; // horizontal display + USHORT usH_SyncStart; // horozontal Sync start + USHORT usH_SyncWidth; // horizontal Sync width + USHORT usV_Total; // vertical total + USHORT usV_Disp; // vertical display + USHORT usV_SyncStart; // vertical Sync start + USHORT usV_SyncWidth; // vertical Sync width + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucOverscanRight; // right + UCHAR ucOverscanLeft; // left + UCHAR ucOverscanBottom; // bottom + UCHAR ucOverscanTop; // top + UCHAR ucReserved; +}SET_CRTC_TIMING_PARAMETERS; +#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS + + +typedef struct _ATOM_MODE_TIMING +{ + USHORT usCRTC_H_Total; + USHORT usCRTC_H_Disp; + USHORT usCRTC_H_SyncStart; + USHORT usCRTC_H_SyncWidth; + USHORT usCRTC_V_Total; + USHORT usCRTC_V_Disp; + USHORT usCRTC_V_SyncStart; + USHORT usCRTC_V_SyncWidth; + USHORT usPixelClock; //in 10Khz unit + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + USHORT usCRTC_OverscanRight; + USHORT usCRTC_OverscanLeft; + USHORT usCRTC_OverscanBottom; + USHORT usCRTC_OverscanTop; + USHORT usReserve; + UCHAR ucInternalModeNumber; + UCHAR ucRefreshRate; +}ATOM_MODE_TIMING; + + +typedef struct _ATOM_DTD_FORMAT +{ + USHORT usPixClk; + USHORT usHActive; + USHORT usHBlanking_Time; + USHORT usVActive; + USHORT usVBlanking_Time; + USHORT usHSyncOffset; + USHORT usHSyncWidth; + USHORT usVSyncOffset; + USHORT usVSyncWidth; + USHORT usImageHSize; + USHORT usImageVSize; + UCHAR ucHBorder; + UCHAR ucVBorder; + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + UCHAR ucReserved1; + UCHAR ucReserved2; +}ATOM_DTD_FORMAT; + +#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 +#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 +#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 +#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 + +/****************************LVDS Info Table Definitions **********************/ +//ucTableFormatRevision=1 +//ucTableContentRevision=1 +typedef struct _ATOM_LVDS_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_DTD_FORMAT sLCDTiming; + USHORT usModePatchTableOffset; + USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. + USHORT usOffDelayInMs; + UCHAR ucPowerSequenceDigOntoDEin10Ms; + UCHAR ucPowerSequenceDEtoBLOnin10Ms; + UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} + // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} + // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} + // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} + UCHAR ucPanelDefaultRefreshRate; + UCHAR ucPanelIdentification; + UCHAR ucSS_Id; +}ATOM_LVDS_INFO; + +//ucTableFormatRevision=1 +//ucTableContentRevision=2 +typedef struct _ATOM_LVDS_INFO_V12 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_DTD_FORMAT sLCDTiming; + USHORT usExtInfoTableOffset; + USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. + USHORT usOffDelayInMs; + UCHAR ucPowerSequenceDigOntoDEin10Ms; + UCHAR ucPowerSequenceDEtoBLOnin10Ms; + UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} + // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} + // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} + // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} + UCHAR ucPanelDefaultRefreshRate; + UCHAR ucPanelIdentification; + UCHAR ucSS_Id; + USHORT usLCDVenderID; + USHORT usLCDProductID; + UCHAR ucLCDPanel_SpecialHandlingCap; + UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable + UCHAR ucReserved[2]; +}ATOM_LVDS_INFO_V12; + +#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 + +typedef struct _ATOM_PATCH_RECORD_MODE +{ + UCHAR ucRecordType; + USHORT usHDisp; + USHORT usVDisp; +}ATOM_PATCH_RECORD_MODE; + +typedef struct _ATOM_LCD_RTS_RECORD +{ + UCHAR ucRecordType; + UCHAR ucRTSValue; +}ATOM_LCD_RTS_RECORD; + +//!! If the record below exits, it shoud always be the first record for easy use in command table!!! +typedef struct _ATOM_LCD_MODE_CONTROL_CAP +{ + UCHAR ucRecordType; + USHORT usLCDCap; +}ATOM_LCD_MODE_CONTROL_CAP; + +#define LCD_MODE_CAP_BL_OFF 1 +#define LCD_MODE_CAP_CRTC_OFF 2 +#define LCD_MODE_CAP_PANEL_OFF 4 + +typedef struct _ATOM_FAKE_EDID_PATCH_RECORD +{ + UCHAR ucRecordType; + UCHAR ucFakeEDIDLength; + UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. +} ATOM_FAKE_EDID_PATCH_RECORD; + +typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD +{ + UCHAR ucRecordType; + USHORT usHSize; + USHORT usVSize; +}ATOM_PANEL_RESOLUTION_PATCH_RECORD; + +#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 +#define LCD_RTS_RECORD_TYPE 2 +#define LCD_CAP_RECORD_TYPE 3 +#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 +#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 +#define ATOM_RECORD_END_TYPE 0xFF + +/****************************Spread Spectrum Info Table Definitions **********************/ + +//ucTableFormatRevision=1 +//ucTableContentRevision=2 +typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT +{ + USHORT usSpreadSpectrumPercentage; + UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD + UCHAR ucSS_Step; + UCHAR ucSS_Delay; + UCHAR ucSS_Id; + UCHAR ucRecommandedRef_Div; + UCHAR ucSS_Range; //it was reserved for V11 +}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; + +#define ATOM_MAX_SS_ENTRY 16 +#define ATOM_DP_SS_ID1 0x0f1 // SS modulation freq=30k +#define ATOM_DP_SS_ID2 0x0f2 // SS modulation freq=33k + + +#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 +#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 +#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 +#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 +#define ATOM_INTERNAL_SS_MASK 0x00000000 +#define ATOM_EXTERNAL_SS_MASK 0x00000002 +#define EXEC_SS_STEP_SIZE_SHIFT 2 +#define EXEC_SS_DELAY_SHIFT 4 +#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 + +typedef struct _ATOM_SPREAD_SPECTRUM_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; +}ATOM_SPREAD_SPECTRUM_INFO; + + + + +//ucTVBootUpDefaultStd definiton: + +//ATOM_TV_NTSC 1 +//ATOM_TV_NTSCJ 2 +//ATOM_TV_PAL 3 +//ATOM_TV_PALM 4 +//ATOM_TV_PALCN 5 +//ATOM_TV_PALN 6 +//ATOM_TV_PAL60 7 +//ATOM_TV_SECAM 8 + + +//ucTVSuppportedStd definition: +#define NTSC_SUPPORT 0x1 +#define NTSCJ_SUPPORT 0x2 + +#define PAL_SUPPORT 0x4 +#define PALM_SUPPORT 0x8 +#define PALCN_SUPPORT 0x10 +#define PALN_SUPPORT 0x20 +#define PAL60_SUPPORT 0x40 +#define SECAM_SUPPORT 0x80 + +#define MAX_SUPPORTED_TV_TIMING 2 + +typedef struct _ATOM_ANALOG_TV_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucTV_SuppportedStandard; + UCHAR ucTV_BootUpDefaultStandard; + UCHAR ucExt_TV_ASIC_ID; + UCHAR ucExt_TV_ASIC_SlaveAddr; + ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; +}ATOM_ANALOG_TV_INFO; + + +/**************************************************************************/ +// VRAM usage and their defintions + +// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. +// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. +// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! +// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR +// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX + +#ifndef VESA_MEMORY_IN_64K_BLOCK +#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) +#endif + +#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes +#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes +#define ATOM_HWICON_INFOTABLE_SIZE 32 +#define MAX_DTD_MODE_IN_VRAM 6 +#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) +#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) +#define DFP_ENCODER_TYPE_OFFSET 0x80 +#define DP_ENCODER_LANE_NUMBER 0x84 +#define DP_ENCODER_LINK_RATE 0x88 + +#define ATOM_HWICON1_SURFACE_ADDR 0 +#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) +#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) +#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) +#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_TV2_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_TV2_DTD_MODE_TBL_ADDR (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_TV2_STD_MODE_TBL_ADDR (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DFP2_EDID_ADDR (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) + +#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256) +#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512 + +//The size below is in Kb! +#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) + +#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L +#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 +#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 +#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 + +#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 + +typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO +{ + ULONG ulStartAddrUsedByFirmware; + USHORT usFirmwareUseInKb; + USHORT usReserved; +}ATOM_FIRMWARE_VRAM_RESERVE_INFO; + +typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; +}ATOM_VRAM_USAGE_BY_FIRMWARE; + +/**************************************************************************/ +//GPIO Pin lut table definition +typedef struct _ATOM_GPIO_PIN_ASSIGNMENT +{ + USHORT usGpioPin_AIndex; + UCHAR ucGpioPinBitShift; + UCHAR ucGPIO_ID; +}ATOM_GPIO_PIN_ASSIGNMENT; + +typedef struct _ATOM_GPIO_PIN_LUT +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; +}ATOM_GPIO_PIN_LUT; + +/**************************************************************************/ + + +#define GPIO_PIN_ACTIVE_HIGH 0x1 + +#define MAX_SUPPORTED_CV_STANDARDS 5 + +// definitions for ATOM_D_INFO.ucSettings +#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] +#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out +#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] + +typedef struct _ATOM_GPIO_INFO +{ + USHORT usAOffset; + UCHAR ucSettings; + UCHAR ucReserved; +}ATOM_GPIO_INFO; + +// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) +#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 + +// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i +#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; +#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] + +// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode +//Line 3 out put 5V. +#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 +#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 +#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 + +//Line 3 out put 2.2V +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 + +//Line 3 out put 0V +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 + +#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] + +#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 + +//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. +#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. +#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. + + +typedef struct _ATOM_COMPONENT_VIDEO_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMask_PinRegisterIndex; + USHORT usEN_PinRegisterIndex; + USHORT usY_PinRegisterIndex; + USHORT usA_PinRegisterIndex; + UCHAR ucBitShift; + UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low + ATOM_DTD_FORMAT sReserved; // must be zeroed out + UCHAR ucMiscInfo; + UCHAR uc480i; + UCHAR uc480p; + UCHAR uc720p; + UCHAR uc1080i; + UCHAR ucLetterBoxMode; + UCHAR ucReserved[3]; + UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector + ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; + ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; +}ATOM_COMPONENT_VIDEO_INFO; + +//ucTableFormatRevision=2 +//ucTableContentRevision=1 +typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucMiscInfo; + UCHAR uc480i; + UCHAR uc480p; + UCHAR uc720p; + UCHAR uc1080i; + UCHAR ucReserved; + UCHAR ucLetterBoxMode; + UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector + ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; + ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; +}ATOM_COMPONENT_VIDEO_INFO_V21; + +#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 + +/**************************************************************************/ +//Object table starts here +typedef struct _ATOM_OBJECT_HEADER +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + USHORT usConnectorObjectTableOffset; + USHORT usRouterObjectTableOffset; + USHORT usEncoderObjectTableOffset; + USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. + USHORT usDisplayPathTableOffset; +}ATOM_OBJECT_HEADER; + + +typedef struct _ATOM_DISPLAY_OBJECT_PATH +{ + USHORT usDeviceTag; //supported device + USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH + USHORT usConnObjectId; //Connector Object ID + USHORT usGPUObjectId; //GPU ID + USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. +}ATOM_DISPLAY_OBJECT_PATH; + +typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE +{ + UCHAR ucNumOfDispPath; + UCHAR ucVersion; + UCHAR ucPadding[2]; + ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; +}ATOM_DISPLAY_OBJECT_PATH_TABLE; + + +typedef struct _ATOM_OBJECT //each object has this structure +{ + USHORT usObjectID; + USHORT usSrcDstTableOffset; + USHORT usRecordOffset; //this pointing to a bunch of records defined below + USHORT usReserved; +}ATOM_OBJECT; + +typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure +{ + UCHAR ucNumberOfObjects; + UCHAR ucPadding[3]; + ATOM_OBJECT asObjects[1]; +}ATOM_OBJECT_TABLE; + +typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure +{ + UCHAR ucNumberOfSrc; + USHORT usSrcObjectID[1]; + UCHAR ucNumberOfDst; + USHORT usDstObjectID[1]; +}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; + + +//Related definitions, all records are differnt but they have a commond header +typedef struct _ATOM_COMMON_RECORD_HEADER +{ + UCHAR ucRecordType; //An emun to indicate the record type + UCHAR ucRecordSize; //The size of the whole record in byte +}ATOM_COMMON_RECORD_HEADER; + + +#define ATOM_I2C_RECORD_TYPE 1 +#define ATOM_HPD_INT_RECORD_TYPE 2 +#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 +#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 +#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE +#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE +#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 +#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE +#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 +#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 +#define ATOM_CONNECTOR_CF_RECORD_TYPE 11 +#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 +#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 +#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 +#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 + +//Must be updated when new record type is added,equal to that record definition! +#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_CF_RECORD_TYPE + +typedef struct _ATOM_I2C_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + ATOM_I2C_ID_CONFIG sucI2cId; + UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC +}ATOM_I2C_RECORD; + +typedef struct _ATOM_HPD_INT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info + UCHAR ucPluggged_PinState; +}ATOM_HPD_INT_RECORD; + + +typedef struct _ATOM_OUTPUT_PROTECTION_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucProtectionFlag; + UCHAR ucReserved; +}ATOM_OUTPUT_PROTECTION_RECORD; + +typedef struct _ATOM_CONNECTOR_DEVICE_TAG +{ + ULONG ulACPIDeviceEnum; //Reserved for now + USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" + USHORT usPadding; +}ATOM_CONNECTOR_DEVICE_TAG; + +typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucNumberOfDevice; + UCHAR ucReserved; + ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation +}ATOM_CONNECTOR_DEVICE_TAG_RECORD; + + +typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucConfigGPIOID; + UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in + UCHAR ucFlowinGPIPID; + UCHAR ucExtInGPIPID; +}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; + +typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucCTL1GPIO_ID; + UCHAR ucCTL1GPIOState; //Set to 1 when it's active high + UCHAR ucCTL2GPIO_ID; + UCHAR ucCTL2GPIOState; //Set to 1 when it's active high + UCHAR ucCTL3GPIO_ID; + UCHAR ucCTL3GPIOState; //Set to 1 when it's active high + UCHAR ucCTLFPGA_IN_ID; + UCHAR ucPadding[3]; +}ATOM_ENCODER_FPGA_CONTROL_RECORD; + +typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info + UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected +}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; + +typedef struct _ATOM_JTAG_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucTMSGPIO_ID; + UCHAR ucTMSGPIOState; //Set to 1 when it's active high + UCHAR ucTCKGPIO_ID; + UCHAR ucTCKGPIOState; //Set to 1 when it's active high + UCHAR ucTDOGPIO_ID; + UCHAR ucTDOGPIOState; //Set to 1 when it's active high + UCHAR ucTDIGPIO_ID; + UCHAR ucTDIGPIOState; //Set to 1 when it's active high + UCHAR ucPadding[2]; +}ATOM_JTAG_RECORD; + + +//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually +typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR +{ + UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table + UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin +}ATOM_GPIO_PIN_CONTROL_PAIR; + +typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucFlags; // Future expnadibility + UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object + ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins +}ATOM_OBJECT_GPIO_CNTL_RECORD; + +//Definitions for GPIO pin state +#define GPIO_PIN_TYPE_INPUT 0x00 +#define GPIO_PIN_TYPE_OUTPUT 0x10 +#define GPIO_PIN_TYPE_HW_CONTROL 0x20 + +//For GPIO_PIN_TYPE_OUTPUT the following is defined +#define GPIO_PIN_OUTPUT_STATE_MASK 0x01 +#define GPIO_PIN_OUTPUT_STATE_SHIFT 0 +#define GPIO_PIN_STATE_ACTIVE_LOW 0x0 +#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 + +typedef struct _ATOM_ENCODER_DVO_CF_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + ULONG ulStrengthControl; // DVOA strength control for CF + UCHAR ucPadding[2]; +}ATOM_ENCODER_DVO_CF_RECORD; + +// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle +#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 +#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 + +typedef struct _ATOM_CONNECTOR_CF_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + USHORT usMaxPixClk; + UCHAR ucFlowCntlGpioId; + UCHAR ucSwapCntlGpioId; + UCHAR ucConnectedDvoBundle; + UCHAR ucPadding; +}ATOM_CONNECTOR_CF_RECORD; + +typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + ATOM_DTD_FORMAT asTiming; +}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; + +typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE + UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A + UCHAR ucReserved; +}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; + + +typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state + UCHAR ucMuxControlPin; + UCHAR ucMuxState[2]; //for alligment purpose +}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; + +typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD +{ + ATOM_COMMON_RECORD_HEADER sheader; + UCHAR ucMuxType; + UCHAR ucMuxControlPin; + UCHAR ucMuxState[2]; //for alligment purpose +}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; + +// define ucMuxType +#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f +#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 + +/**************************************************************************/ +//ASIC voltage data table starts here + +typedef struct _ATOM_VOLTAGE_INFO_HEADER +{ + USHORT usVDDCBaseLevel; //In number of 50mv unit + USHORT usReserved; //For possible extension table offset + UCHAR ucNumOfVoltageEntries; + UCHAR ucBytesPerVoltageEntry; + UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit + UCHAR ucDefaultVoltageEntry; + UCHAR ucVoltageControlI2cLine; + UCHAR ucVoltageControlAddress; + UCHAR ucVoltageControlOffset; +}ATOM_VOLTAGE_INFO_HEADER; + +typedef struct _ATOM_VOLTAGE_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_INFO_HEADER viHeader; + UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry +}ATOM_VOLTAGE_INFO; + + +typedef struct _ATOM_VOLTAGE_FORMULA +{ + USHORT usVoltageBaseLevel; // In number of 1mv unit + USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit + UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage + UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv + UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep + UCHAR ucReserved; + UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries +}ATOM_VOLTAGE_FORMULA; + +typedef struct _ATOM_VOLTAGE_CONTROL +{ + UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine + UCHAR ucVoltageControlI2cLine; + UCHAR ucVoltageControlAddress; + UCHAR ucVoltageControlOffset; + USHORT usGpioPin_AIndex; //GPIO_PAD register index + UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff + UCHAR ucReserved; +}ATOM_VOLTAGE_CONTROL; + +// Define ucVoltageControlId +#define VOLTAGE_CONTROLLED_BY_HW 0x00 +#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F +#define VOLTAGE_CONTROLLED_BY_GPIO 0x80 +#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage +#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI +#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage +#define VOLTAGE_CONTROL_ID_DS4402 0x04 + +typedef struct _ATOM_VOLTAGE_OBJECT +{ + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucSize; //Size of Object + ATOM_VOLTAGE_CONTROL asControl; //describ how to control + ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID +}ATOM_VOLTAGE_OBJECT; + +typedef struct _ATOM_VOLTAGE_OBJECT_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control +}ATOM_VOLTAGE_OBJECT_INFO; + +typedef struct _ATOM_LEAKID_VOLTAGE +{ + UCHAR ucLeakageId; + UCHAR ucReserved; + USHORT usVoltage; +}ATOM_LEAKID_VOLTAGE; + +typedef struct _ATOM_ASIC_PROFILE_VOLTAGE +{ + UCHAR ucProfileId; + UCHAR ucReserved; + USHORT usSize; + USHORT usEfuseSpareStartAddr; + USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, + ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage +}ATOM_ASIC_PROFILE_VOLTAGE; + +//ucProfileId +#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 +#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 +#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 + +typedef struct _ATOM_ASIC_PROFILING_INFO +{ + ATOM_COMMON_TABLE_HEADER asHeader; + ATOM_ASIC_PROFILE_VOLTAGE asVoltage; +}ATOM_ASIC_PROFILING_INFO; + +typedef struct _ATOM_POWER_SOURCE_OBJECT +{ + UCHAR ucPwrSrcId; // Power source + UCHAR ucPwrSensorType; // GPIO, I2C or none + UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id + UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect + UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect + UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect + UCHAR ucPwrSensActiveState; // high active or low active + UCHAR ucReserve[3]; // reserve + USHORT usSensPwr; // in unit of watt +}ATOM_POWER_SOURCE_OBJECT; + +typedef struct _ATOM_POWER_SOURCE_INFO +{ + ATOM_COMMON_TABLE_HEADER asHeader; + UCHAR asPwrbehave[16]; + ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; +}ATOM_POWER_SOURCE_INFO; + + +//Define ucPwrSrcId +#define POWERSOURCE_PCIE_ID1 0x00 +#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 +#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 +#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 +#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 + +//define ucPwrSensorId +#define POWER_SENSOR_ALWAYS 0x00 +#define POWER_SENSOR_GPIO 0x01 +#define POWER_SENSOR_I2C 0x02 + +/**************************************************************************/ +// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design +//Memory SS Info Table +//Define Memory Clock SS chip ID +#define ICS91719 1 +#define ICS91720 2 + +//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol +typedef struct _ATOM_I2C_DATA_RECORD +{ + UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" + UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually +}ATOM_I2C_DATA_RECORD; + + +//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information +typedef struct _ATOM_I2C_DEVICE_SETUP_INFO +{ + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. + UCHAR ucSSChipID; //SS chip being used + UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip + UCHAR ucNumOfI2CDataRecords; //number of data block + ATOM_I2C_DATA_RECORD asI2CData[1]; +}ATOM_I2C_DEVICE_SETUP_INFO; + +//========================================================================================== +typedef struct _ATOM_ASIC_MVDD_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; +}ATOM_ASIC_MVDD_INFO; + +//========================================================================================== +#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO + +//========================================================================================== +/**************************************************************************/ + +typedef struct _ATOM_ASIC_SS_ASSIGNMENT +{ + ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz + USHORT usSpreadSpectrumPercentage; //in unit of 0.01% + USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq + UCHAR ucClockIndication; //Indicate which clock source needs SS + UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. + UCHAR ucReserved[2]; +}ATOM_ASIC_SS_ASSIGNMENT; + +//Define ucSpreadSpectrumType +#define ASIC_INTERNAL_MEMORY_SS 1 +#define ASIC_INTERNAL_ENGINE_SS 2 +#define ASIC_INTERNAL_UVD_SS 3 + +typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; +}ATOM_ASIC_INTERNAL_SS_INFO; + +//==============================Scratch Pad Definition Portion=============================== +#define ATOM_DEVICE_CONNECT_INFO_DEF 0 +#define ATOM_ROM_LOCATION_DEF 1 +#define ATOM_TV_STANDARD_DEF 2 +#define ATOM_ACTIVE_INFO_DEF 3 +#define ATOM_LCD_INFO_DEF 4 +#define ATOM_DOS_REQ_INFO_DEF 5 +#define ATOM_ACC_CHANGE_INFO_DEF 6 +#define ATOM_DOS_MODE_INFO_DEF 7 +#define ATOM_I2C_CHANNEL_STATUS_DEF 8 +#define ATOM_I2C_CHANNEL_STATUS1_DEF 9 + + +// BIOS_0_SCRATCH Definition +#define ATOM_S0_CRT1_MONO 0x00000001L +#define ATOM_S0_CRT1_COLOR 0x00000002L +#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) + +#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L +#define ATOM_S0_TV1_SVIDEO_A 0x00000008L +#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) + +#define ATOM_S0_CV_A 0x00000010L +#define ATOM_S0_CV_DIN_A 0x00000020L +#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) + + +#define ATOM_S0_CRT2_MONO 0x00000100L +#define ATOM_S0_CRT2_COLOR 0x00000200L +#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) + +#define ATOM_S0_TV1_COMPOSITE 0x00000400L +#define ATOM_S0_TV1_SVIDEO 0x00000800L +#define ATOM_S0_TV1_SCART 0x00004000L +#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) + +#define ATOM_S0_CV 0x00001000L +#define ATOM_S0_CV_DIN 0x00002000L +#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) + + +#define ATOM_S0_DFP1 0x00010000L +#define ATOM_S0_DFP2 0x00020000L +#define ATOM_S0_LCD1 0x00040000L +#define ATOM_S0_LCD2 0x00080000L +#define ATOM_S0_TV2 0x00100000L +#define ATOM_S0_DFP3 0x00200000L + +#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with + // the FAD/HDP reg access bug. Bit is read by DAL + +#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L +#define ATOM_S0_THERMAL_STATE_SHIFT 26 + +#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L +#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 + +#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 +#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 +#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 + +//Byte aligned defintion for BIOS usage +#define ATOM_S0_CRT1_MONOb0 0x01 +#define ATOM_S0_CRT1_COLORb0 0x02 +#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) + +#define ATOM_S0_TV1_COMPOSITEb0 0x04 +#define ATOM_S0_TV1_SVIDEOb0 0x08 +#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) + +#define ATOM_S0_CVb0 0x10 +#define ATOM_S0_CV_DINb0 0x20 +#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) + +#define ATOM_S0_CRT2_MONOb1 0x01 +#define ATOM_S0_CRT2_COLORb1 0x02 +#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) + +#define ATOM_S0_TV1_COMPOSITEb1 0x04 +#define ATOM_S0_TV1_SVIDEOb1 0x08 +#define ATOM_S0_TV1_SCARTb1 0x40 +#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) + +#define ATOM_S0_CVb1 0x10 +#define ATOM_S0_CV_DINb1 0x20 +#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) + +#define ATOM_S0_DFP1b2 0x01 +#define ATOM_S0_DFP2b2 0x02 +#define ATOM_S0_LCD1b2 0x04 +#define ATOM_S0_LCD2b2 0x08 +#define ATOM_S0_TV2b2 0x10 +#define ATOM_S0_DFP3b2 0x20 + +#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C +#define ATOM_S0_THERMAL_STATE_SHIFTb3 2 + +#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 +#define ATOM_S0_LCD1_SHIFT 18 + +// BIOS_1_SCRATCH Definition +#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL +#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L + + +// BIOS_2_SCRATCH Definition +#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL +#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L +#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 + +#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L +#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L +#define ATOM_S2_TV1_DPMS_STATE 0x00040000L +#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L +#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L +#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L +#define ATOM_S2_TV2_DPMS_STATE 0x00400000L +#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L +#define ATOM_S2_CV_DPMS_STATE 0x01000000L +#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L + +#define ATOM_S2_DEVICE_DPMS_STATE (ATOM_S2_CRT1_DPMS_STATE+ATOM_S2_LCD1_DPMS_STATE+ATOM_S2_TV1_DPMS_STATE+\ + ATOM_S2_DFP1I_DPMS_STATE+ATOM_S2_CRT2_DPMS_STATE+ATOM_S2_LCD2_DPMS_STATE+\ + ATOM_S2_TV2_DPMS_STATE+ATOM_S2_DFP1X_DPMS_STATE+ATOM_S2_CV_DPMS_STATE+\ + ATOM_S2_DFP3_DPMS_STATE) + + +#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L +#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 +#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L + +#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L + +#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 +#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 +#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 +#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 +#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 +#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L + + +//Byte aligned defintion for BIOS usage +#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F +#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF +#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 +#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 +#define ATOM_S2_TV1_DPMS_STATEb2 0x04 +#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 +#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 +#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 +#define ATOM_S2_TV2_DPMS_STATEb2 0x40 +#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 +#define ATOM_S2_CV_DPMS_STATEb3 0x01 +#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 + +#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF +#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C +#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 +#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 +#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 + + +// BIOS_3_SCRATCH Definition +#define ATOM_S3_CRT1_ACTIVE 0x00000001L +#define ATOM_S3_LCD1_ACTIVE 0x00000002L +#define ATOM_S3_TV1_ACTIVE 0x00000004L +#define ATOM_S3_DFP1_ACTIVE 0x00000008L +#define ATOM_S3_CRT2_ACTIVE 0x00000010L +#define ATOM_S3_LCD2_ACTIVE 0x00000020L +#define ATOM_S3_TV2_ACTIVE 0x00000040L +#define ATOM_S3_DFP2_ACTIVE 0x00000080L +#define ATOM_S3_CV_ACTIVE 0x00000100L +#define ATOM_S3_DFP3_ACTIVE 0x00000200L + +#define ATOM_S3_DEVICE_ACTIVE_MASK 0x000003FFL + +#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L +#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L +#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L +#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L +#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L +#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L +#define ATOM_S3_TV2_CRTC_ACTIVE 0x00400000L +#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L +#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L +#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L + +#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x03FF0000L +#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L +#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L +#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L + +//Byte aligned defintion for BIOS usage +#define ATOM_S3_CRT1_ACTIVEb0 0x01 +#define ATOM_S3_LCD1_ACTIVEb0 0x02 +#define ATOM_S3_TV1_ACTIVEb0 0x04 +#define ATOM_S3_DFP1_ACTIVEb0 0x08 +#define ATOM_S3_CRT2_ACTIVEb0 0x10 +#define ATOM_S3_LCD2_ACTIVEb0 0x20 +#define ATOM_S3_TV2_ACTIVEb0 0x40 +#define ATOM_S3_DFP2_ACTIVEb0 0x80 +#define ATOM_S3_CV_ACTIVEb1 0x01 +#define ATOM_S3_DFP3_ACTIVEb1 0x02 + +#define ATOM_S3_ACTIVE_CRTC1w0 0x3FF + +#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 +#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 +#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 +#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 +#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 +#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 +#define ATOM_S3_TV2_CRTC_ACTIVEb2 0x40 +#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 +#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 +#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 + +#define ATOM_S3_ACTIVE_CRTC2w1 0x3FF + +#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 +#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 +#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 + +// BIOS_4_SCRATCH Definition +#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL +#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L +#define ATOM_S4_LCD1_REFRESH_SHIFT 8 + + +//Byte aligned defintion for BIOS usage +#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF +#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 +#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 + + +// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! +#define ATOM_S5_DOS_REQ_CRT1b0 0x01 +#define ATOM_S5_DOS_REQ_LCD1b0 0x02 +#define ATOM_S5_DOS_REQ_TV1b0 0x04 +#define ATOM_S5_DOS_REQ_DFP1b0 0x08 +#define ATOM_S5_DOS_REQ_CRT2b0 0x10 +#define ATOM_S5_DOS_REQ_LCD2b0 0x20 +#define ATOM_S5_DOS_REQ_TV2b0 0x40 +#define ATOM_S5_DOS_REQ_DFP2b0 0x80 +#define ATOM_S5_DOS_REQ_CVb1 0x01 +#define ATOM_S5_DOS_REQ_DFP3b1 0x02 + +#define ATOM_S5_DOS_REQ_DEVICEw0 0x03FF + +#define ATOM_S5_DOS_REQ_CRT1 0x0001 +#define ATOM_S5_DOS_REQ_LCD1 0x0002 +#define ATOM_S5_DOS_REQ_TV1 0x0004 +#define ATOM_S5_DOS_REQ_DFP1 0x0008 +#define ATOM_S5_DOS_REQ_CRT2 0x0010 +#define ATOM_S5_DOS_REQ_LCD2 0x0020 +#define ATOM_S5_DOS_REQ_TV2 0x0040 +#define ATOM_S5_DOS_REQ_DFP2 0x0080 +#define ATOM_S5_DOS_REQ_CV 0x0100 +#define ATOM_S5_DOS_REQ_DFP3 0x0200 + +#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 +#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 +#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 +#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 +#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ + (ATOM_S5_DOS_FORCE_CVb3<<8)) + +// BIOS_6_SCRATCH Definition +#define ATOM_S6_DEVICE_CHANGE 0x00000001L +#define ATOM_S6_SCALER_CHANGE 0x00000002L +#define ATOM_S6_LID_CHANGE 0x00000004L +#define ATOM_S6_DOCKING_CHANGE 0x00000008L +#define ATOM_S6_ACC_MODE 0x00000010L +#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L +#define ATOM_S6_LID_STATE 0x00000040L +#define ATOM_S6_DOCK_STATE 0x00000080L +#define ATOM_S6_CRITICAL_STATE 0x00000100L +#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L +#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L +#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L +#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD +#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD + +#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion +#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion + + +#define ATOM_S6_ACC_REQ_CRT1 0x00010000L +#define ATOM_S6_ACC_REQ_LCD1 0x00020000L +#define ATOM_S6_ACC_REQ_TV1 0x00040000L +#define ATOM_S6_ACC_REQ_DFP1 0x00080000L +#define ATOM_S6_ACC_REQ_CRT2 0x00100000L +#define ATOM_S6_ACC_REQ_LCD2 0x00200000L +#define ATOM_S6_ACC_REQ_TV2 0x00400000L +#define ATOM_S6_ACC_REQ_DFP2 0x00800000L +#define ATOM_S6_ACC_REQ_CV 0x01000000L +#define ATOM_S6_ACC_REQ_DFP3 0x02000000L + +#define ATOM_S6_ACC_REQ_MASK 0x03FF0000L +#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L +#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L +#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L +#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L + +//Byte aligned defintion for BIOS usage +#define ATOM_S6_DEVICE_CHANGEb0 0x01 +#define ATOM_S6_SCALER_CHANGEb0 0x02 +#define ATOM_S6_LID_CHANGEb0 0x04 +#define ATOM_S6_DOCKING_CHANGEb0 0x08 +#define ATOM_S6_ACC_MODEb0 0x10 +#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 +#define ATOM_S6_LID_STATEb0 0x40 +#define ATOM_S6_DOCK_STATEb0 0x80 +#define ATOM_S6_CRITICAL_STATEb1 0x01 +#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 +#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 +#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 +#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 +#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 + +#define ATOM_S6_ACC_REQ_CRT1b2 0x01 +#define ATOM_S6_ACC_REQ_LCD1b2 0x02 +#define ATOM_S6_ACC_REQ_TV1b2 0x04 +#define ATOM_S6_ACC_REQ_DFP1b2 0x08 +#define ATOM_S6_ACC_REQ_CRT2b2 0x10 +#define ATOM_S6_ACC_REQ_LCD2b2 0x20 +#define ATOM_S6_ACC_REQ_TV2b2 0x40 +#define ATOM_S6_ACC_REQ_DFP2b2 0x80 +#define ATOM_S6_ACC_REQ_CVb3 0x01 +#define ATOM_S6_ACC_REQ_DFP3b3 0x02 + +#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 +#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 +#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 +#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 +#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 + +#define ATOM_S6_DEVICE_CHANGE_SHIFT 0 +#define ATOM_S6_SCALER_CHANGE_SHIFT 1 +#define ATOM_S6_LID_CHANGE_SHIFT 2 +#define ATOM_S6_DOCKING_CHANGE_SHIFT 3 +#define ATOM_S6_ACC_MODE_SHIFT 4 +#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 +#define ATOM_S6_LID_STATE_SHIFT 6 +#define ATOM_S6_DOCK_STATE_SHIFT 7 +#define ATOM_S6_CRITICAL_STATE_SHIFT 8 +#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 +#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 +#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 +#define ATOM_S6_REQ_SCALER_SHIFT 12 +#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 +#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 +#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 +#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 +#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 +#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 +#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 + +// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! +#define ATOM_S7_DOS_MODE_TYPEb0 0x03 +#define ATOM_S7_DOS_MODE_VGAb0 0x00 +#define ATOM_S7_DOS_MODE_VESAb0 0x01 +#define ATOM_S7_DOS_MODE_EXTb0 0x02 +#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C +#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 +#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 +#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF + +#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 + +// BIOS_8_SCRATCH Definition +#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF +#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 + +#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 +#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 + +// BIOS_9_SCRATCH Definition +#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK +#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF +#endif +#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK +#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 +#endif +#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT +#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 +#endif +#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT +#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 +#endif + + +#define ATOM_FLAG_SET 0x20 +#define ATOM_FLAG_CLEAR 0 +#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) +#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) + +#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) + +#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) + +#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) + +#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) + +#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) + +#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) +#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) + +#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) + +#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) + +#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) +#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) +#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) +#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) + +/****************************************************************************/ +//Portion II: Definitinos only used in Driver +/****************************************************************************/ + +// Macros used by driver + +#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) + +#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) +#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) + +#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION +#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION + +/****************************************************************************/ +//Portion III: Definitinos only used in VBIOS +/****************************************************************************/ +#define ATOM_DAC_SRC 0x80 +#define ATOM_SRC_DAC1 0 +#define ATOM_SRC_DAC2 0x80 + + +#ifdef UEFI_BUILD + #define USHORT UTEMP +#endif + +typedef struct _MEMORY_PLLINIT_PARAMETERS +{ + ULONG ulTargetMemoryClock; //In 10Khz unit + UCHAR ucAction; //not define yet + UCHAR ucFbDiv_Hi; //Fbdiv Hi byte + UCHAR ucFbDiv; //FB value + UCHAR ucPostDiv; //Post div +}MEMORY_PLLINIT_PARAMETERS; + +#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS + + +#define GPIO_PIN_WRITE 0x01 +#define GPIO_PIN_READ 0x00 + +typedef struct _GPIO_PIN_CONTROL_PARAMETERS +{ + UCHAR ucGPIO_ID; //return value, read from GPIO pins + UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update + UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask + UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write +}GPIO_PIN_CONTROL_PARAMETERS; + +typedef struct _ENABLE_SCALER_PARAMETERS +{ + UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 + UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION + UCHAR ucPadding[2]; +}ENABLE_SCALER_PARAMETERS; +#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS + +//ucEnable: +#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 +#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 +#define SCALER_ENABLE_2TAP_ALPHA_MODE 2 +#define SCALER_ENABLE_MULTITAP_MODE 3 + +typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS +{ + ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position + UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset + UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset + UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE +}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; + +typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION +{ + ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; + ENABLE_CRTC_PARAMETERS sReserved; +}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; + +typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS +{ + USHORT usHight; // Image Hight + USHORT usWidth; // Image Width + UCHAR ucSurface; // Surface 1 or 2 + UCHAR ucPadding[3]; +}ENABLE_GRAPH_SURFACE_PARAMETERS; + +typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION +{ + ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; + ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one +}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; + +typedef struct _MEMORY_CLEAN_UP_PARAMETERS +{ + USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address + USHORT usMemorySize; //8Kb blocks aligned +}MEMORY_CLEAN_UP_PARAMETERS; +#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS + +typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS +{ + USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC + USHORT usY_Size; +}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; + +typedef struct _INDIRECT_IO_ACCESS +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR IOAccessSequence[256]; +} INDIRECT_IO_ACCESS; + +#define INDIRECT_READ 0x00 +#define INDIRECT_WRITE 0x80 + +#define INDIRECT_IO_MM 0 +#define INDIRECT_IO_PLL 1 +#define INDIRECT_IO_MC 2 +#define INDIRECT_IO_PCIE 3 +#define INDIRECT_IO_PCIEP 4 + +#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ +#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE +#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ +#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE +#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ +#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE +#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ +#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE + +typedef struct _ATOM_OEM_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; +}ATOM_OEM_INFO; + +typedef struct _ATOM_TV_MODE +{ + UCHAR ucVMode_Num; //Video mode number + UCHAR ucTV_Mode_Num; //Internal TV mode number +}ATOM_TV_MODE; + +typedef struct _ATOM_BIOS_INT_TVSTD_MODE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table + USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table + USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table + USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table + USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table +}ATOM_BIOS_INT_TVSTD_MODE; + + +typedef struct _ATOM_TV_MODE_SCALER_PTR +{ + USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients + USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients + UCHAR ucTV_Mode_Num; +}ATOM_TV_MODE_SCALER_PTR; + +typedef struct _ATOM_STANDARD_VESA_TIMING +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_MODE_TIMING aModeTimings[16]; // 16 is not the real array number, just for initial allocation +}ATOM_STANDARD_VESA_TIMING; + + +typedef struct _ATOM_STD_FORMAT +{ + USHORT usSTD_HDisp; + USHORT usSTD_VDisp; + USHORT usSTD_RefreshRate; + USHORT usReserved; +}ATOM_STD_FORMAT; + +typedef struct _ATOM_VESA_TO_EXTENDED_MODE +{ + USHORT usVESA_ModeNumber; + USHORT usExtendedModeNumber; +}ATOM_VESA_TO_EXTENDED_MODE; + +typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT +{ + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; +}ATOM_VESA_TO_INTENAL_MODE_LUT; + +/*************** ATOM Memory Related Data Structure ***********************/ +typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ + UCHAR ucMemoryType; + UCHAR ucMemoryVendor; + UCHAR ucAdjMCId; + UCHAR ucDynClkId; + ULONG ulDllResetClkRange; +}ATOM_MEMORY_VENDOR_BLOCK; + + +typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ + ULONG ulMemClockRange:24; + ULONG ucMemBlkId:8; +}ATOM_MEMORY_SETTING_ID_CONFIG; + +typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS +{ + ATOM_MEMORY_SETTING_ID_CONFIG slAccess; + ULONG ulAccess; +}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; + + +typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ + ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; + ULONG aulMemData[1]; +}ATOM_MEMORY_SETTING_DATA_BLOCK; + + +typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ + USHORT usRegIndex; // MC register index + UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf +}ATOM_INIT_REG_INDEX_FORMAT; + + +typedef struct _ATOM_INIT_REG_BLOCK{ + USHORT usRegIndexTblSize; //size of asRegIndexBuf + USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK + ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; + ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; +}ATOM_INIT_REG_BLOCK; + +#define END_OF_REG_INDEX_BLOCK 0x0ffff +#define END_OF_REG_DATA_BLOCK 0x00000000 +#define ATOM_INIT_REG_MASK_FLAG 0x80 +#define CLOCK_RANGE_HIGHEST 0x00ffffff + +#define VALUE_DWORD SIZEOF ULONG +#define VALUE_SAME_AS_ABOVE 0 +#define VALUE_MASK_DWORD 0x84 + +typedef struct _ATOM_MC_INIT_PARAM_TABLE +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usAdjustARB_SEQDataOffset; + USHORT usMCInitMemTypeTblOffset; + USHORT usMCInitCommonTblOffset; + USHORT usMCInitPowerDownTblOffset; + ULONG ulARB_SEQDataBuf[32]; + ATOM_INIT_REG_BLOCK asMCInitMemType; + ATOM_INIT_REG_BLOCK asMCInitCommon; +}ATOM_MC_INIT_PARAM_TABLE; + + +#define _4Mx16 0x2 +#define _4Mx32 0x3 +#define _8Mx16 0x12 +#define _8Mx32 0x13 +#define _16Mx16 0x22 +#define _16Mx32 0x23 +#define _32Mx16 0x32 + +#define SAMSUNG 0x1 +#define INFINEON 0x2 +#define ELPIDA 0x3 +#define ETRON 0x4 +#define NANYA 0x5 +#define HYNIX 0x6 +#define MOSEL 0x7 +#define WINBOND 0x8 +#define ESMT 0x9 +#define MICRO 0xF + +#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 + +#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF +typedef struct _ATOM_VRAM_MODULE_V1 +{ + ULONG ulReserved; + USHORT usEMRSValue; + USHORT usMRSValue; + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender + UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... + UCHAR ucRow; // Number of Row,in power of 2; + UCHAR ucColumn; // Number of Column,in power of 2; + UCHAR ucBank; // Nunber of Bank; + UCHAR ucRank; // Number of Rank, in power of 2 + UCHAR ucChannelNum; // Number of channel; + UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 + UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; + UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; + UCHAR ucReserved[2]; +}ATOM_VRAM_MODULE_V1; + + +typedef struct _ATOM_VRAM_MODULE_V2 +{ + ULONG ulReserved; + ULONG ulFlags; // To enable/disable functionalities based on memory type + ULONG ulEngineClock; // Override of default engine clock for particular memory type + ULONG ulMemoryClock; // Override of default memory clock for particular memory type + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + USHORT usEMRSValue; + USHORT usMRSValue; + USHORT usReserved; + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed + UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... + UCHAR ucRow; // Number of Row,in power of 2; + UCHAR ucColumn; // Number of Column,in power of 2; + UCHAR ucBank; // Nunber of Bank; + UCHAR ucRank; // Number of Rank, in power of 2 + UCHAR ucChannelNum; // Number of channel; + UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 + UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; + UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; + UCHAR ucRefreshRateFactor; + UCHAR ucReserved[3]; +}ATOM_VRAM_MODULE_V2; + + +typedef struct _ATOM_MEMORY_TIMING_FORMAT +{ + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + USHORT usMRS; // mode register + USHORT usEMRS; // extended mode register + UCHAR ucCL; // CAS latency + UCHAR ucWL; // WRITE Latency + UCHAR uctRAS; // tRAS + UCHAR uctRC; // tRC + UCHAR uctRFC; // tRFC + UCHAR uctRCDR; // tRCDR + UCHAR uctRCDW; // tRCDW + UCHAR uctRP; // tRP + UCHAR uctRRD; // tRRD + UCHAR uctWR; // tWR + UCHAR uctWTR; // tWTR + UCHAR uctPDIX; // tPDIX + UCHAR uctFAW; // tFAW + UCHAR uctAOND; // tAOND + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon + UCHAR ucReserved; // +}ATOM_MEMORY_TIMING_FORMAT; + +#define MEM_TIMING_FLAG_APP_MODE 0x01 // =0 mid clock range =1 high clock range + +typedef struct _ATOM_MEMORY_FORMAT +{ + ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock + USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type + USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type + UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed + UCHAR ucRow; // Number of Row,in power of 2; + UCHAR ucColumn; // Number of Column,in power of 2; + UCHAR ucBank; // Nunber of Bank; + UCHAR ucRank; // Number of Rank, in power of 2 + UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 + UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) + UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms + UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 + UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble + UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc + ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock +}ATOM_MEMORY_FORMAT; + + +typedef struct _ATOM_VRAM_MODULE_V3 +{ + ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination + USHORT usSize; // size of ATOM_VRAM_MODULE_V3 + USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage + USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage + UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module + UCHAR ucChannelNum; // board dependent parameter:Number of channel; + UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit + UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv + UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters + UCHAR ucFlag; // To enable/disable functionalities based on memory type + ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec +}ATOM_VRAM_MODULE_V3; + +//ATOM_VRAM_MODULE_V3.ucFlag +#define Mx_FLAG_RDBI_ENABLE 0x01 +#define Mx_FLAG_WDBI_ENABLE 0x02 +#define Mx_FLAG_DQ_QS_AUTO_CALI 0x04 +#define Mx_FLAG_STROBE_SINGLE_END 0x08 +#define Mx_FLAG_DIS_MEM_TRAINING 0x10 + +//ATOM_VRAM_MODULE_V3.ucNPL_RT +#define NPL_RT_MASK 0x0f +#define BATTERY_ODT_MASK 0xc0 + +#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 + +typedef struct _ATOM_VRAM_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucNumOfVRAMModule; + ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; +}ATOM_VRAM_INFO_V2; + +typedef struct _ATOM_VRAM_INFO_V3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting + USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting + USHORT usRerseved; + UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator + UCHAR ucNumOfVRAMModule; + ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; + ATOM_INIT_REG_BLOCK asMemPatch; // for allocation + // ATOM_INIT_REG_BLOCK aMemAdjust; +}ATOM_VRAM_INFO_V3; + +#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 + +typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator +}ATOM_VRAM_GPIO_DETECTION_INFO; + + +typedef struct _ATOM_MEMORY_TRAINING_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucTrainingLoop; + UCHAR ucReserved[3]; + ATOM_INIT_REG_BLOCK asMemTrainingSetting; +}ATOM_MEMORY_TRAINING_INFO; + + +typedef struct SW_I2C_CNTL_DATA_PARAMETERS +{ + UCHAR ucControl; + UCHAR ucData; + UCHAR ucSatus; + UCHAR ucTemp; +} SW_I2C_CNTL_DATA_PARAMETERS; + +#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS + +typedef struct _SW_I2C_IO_DATA_PARAMETERS +{ + USHORT GPIO_Info; + UCHAR ucAct; + UCHAR ucData; + } SW_I2C_IO_DATA_PARAMETERS; + +#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS + +/****************************SW I2C CNTL DEFINITIONS**********************/ +#define SW_I2C_IO_RESET 0 +#define SW_I2C_IO_GET 1 +#define SW_I2C_IO_DRIVE 2 +#define SW_I2C_IO_SET 3 +#define SW_I2C_IO_START 4 + +#define SW_I2C_IO_CLOCK 0 +#define SW_I2C_IO_DATA 0x80 + +#define SW_I2C_IO_ZERO 0 +#define SW_I2C_IO_ONE 0x100 + +#define SW_I2C_CNTL_READ 0 +#define SW_I2C_CNTL_WRITE 1 +#define SW_I2C_CNTL_START 2 +#define SW_I2C_CNTL_STOP 3 +#define SW_I2C_CNTL_OPEN 4 +#define SW_I2C_CNTL_CLOSE 5 +#define SW_I2C_CNTL_WRITE1BIT 6 + +//==============================VESA definition Portion=============================== +#define VESA_OEM_PRODUCT_REV '01.00' +#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support +#define VESA_MODE_WIN_ATTRIBUTE 7 +#define VESA_WIN_SIZE 64 + +typedef struct _PTR_32_BIT_STRUCTURE +{ + USHORT Offset16; + USHORT Segment16; +} PTR_32_BIT_STRUCTURE; + +typedef union _PTR_32_BIT_UNION +{ + PTR_32_BIT_STRUCTURE SegmentOffset; + ULONG Ptr32_Bit; +} PTR_32_BIT_UNION; + +typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE +{ + UCHAR VbeSignature[4]; + USHORT VbeVersion; + PTR_32_BIT_UNION OemStringPtr; + UCHAR Capabilities[4]; + PTR_32_BIT_UNION VideoModePtr; + USHORT TotalMemory; +} VBE_1_2_INFO_BLOCK_UPDATABLE; + + +typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE +{ + VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; + USHORT OemSoftRev; + PTR_32_BIT_UNION OemVendorNamePtr; + PTR_32_BIT_UNION OemProductNamePtr; + PTR_32_BIT_UNION OemProductRevPtr; +} VBE_2_0_INFO_BLOCK_UPDATABLE; + +typedef union _VBE_VERSION_UNION +{ + VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; + VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; +} VBE_VERSION_UNION; + +typedef struct _VBE_INFO_BLOCK +{ + VBE_VERSION_UNION UpdatableVBE_Info; + UCHAR Reserved[222]; + UCHAR OemData[256]; +} VBE_INFO_BLOCK; + +typedef struct _VBE_FP_INFO +{ + USHORT HSize; + USHORT VSize; + USHORT FPType; + UCHAR RedBPP; + UCHAR GreenBPP; + UCHAR BlueBPP; + UCHAR ReservedBPP; + ULONG RsvdOffScrnMemSize; + ULONG RsvdOffScrnMEmPtr; + UCHAR Reserved[14]; +} VBE_FP_INFO; + +typedef struct _VESA_MODE_INFO_BLOCK +{ +// Mandatory information for all VBE revisions + USHORT ModeAttributes; // dw ? ; mode attributes + UCHAR WinAAttributes; // db ? ; window A attributes + UCHAR WinBAttributes; // db ? ; window B attributes + USHORT WinGranularity; // dw ? ; window granularity + USHORT WinSize; // dw ? ; window size + USHORT WinASegment; // dw ? ; window A start segment + USHORT WinBSegment; // dw ? ; window B start segment + ULONG WinFuncPtr; // dd ? ; real mode pointer to window function + USHORT BytesPerScanLine;// dw ? ; bytes per scan line + +//; Mandatory information for VBE 1.2 and above + USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters + USHORT YResolution; // dw ? ; vertical resolution in pixels or characters + UCHAR XCharSize; // db ? ; character cell width in pixels + UCHAR YCharSize; // db ? ; character cell height in pixels + UCHAR NumberOfPlanes; // db ? ; number of memory planes + UCHAR BitsPerPixel; // db ? ; bits per pixel + UCHAR NumberOfBanks; // db ? ; number of banks + UCHAR MemoryModel; // db ? ; memory model type + UCHAR BankSize; // db ? ; bank size in KB + UCHAR NumberOfImagePages;// db ? ; number of images + UCHAR ReservedForPageFunction;//db 1 ; reserved for page function + +//; Direct Color fields(required for direct/6 and YUV/7 memory models) + UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits + UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask + UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits + UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask + UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits + UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask + UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits + UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask + UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes + +//; Mandatory information for VBE 2.0 and above + ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer + ULONG Reserved_1; // dd 0 ; reserved - always set to 0 + USHORT Reserved_2; // dw 0 ; reserved - always set to 0 + +//; Mandatory information for VBE 3.0 and above + USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes + UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes + UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes + UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) + UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) + UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) + UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) + UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) + UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) + UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) + UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) + ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode + UCHAR Reserved; // db 190 dup (0) +} VESA_MODE_INFO_BLOCK; + +// BIOS function CALLS +#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code +#define ATOM_BIOS_FUNCTION_COP_MODE 0x00 +#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 +#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 +#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 +#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B +#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E +#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F +#define ATOM_BIOS_FUNCTION_STV_STD 0x16 +#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 +#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 + +#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 +#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 +#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 +#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A +#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B +#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 +#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 + +#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D +#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E +#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F +#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 +#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 +#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state +#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state +#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 +#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 +#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported + + +#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS +#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 +#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 +#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. +#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY +#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND +#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF +#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) + +#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L +#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L +#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL + +// structure used for VBIOS only + +//DispOutInfoTable +typedef struct _ASIC_TRANSMITTER_INFO +{ + USHORT usTransmitterObjId; + USHORT usSupportDevice; + UCHAR ucTransmitterCmdTblId; + UCHAR ucConfig; + UCHAR ucEncoderID; //available 1st encoder ( default ) + UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) + UCHAR uc2ndEncoderID; + UCHAR ucReserved; +}ASIC_TRANSMITTER_INFO; + +typedef struct _ASIC_ENCODER_INFO +{ + UCHAR ucEncoderID; + UCHAR ucEncoderConfig; + USHORT usEncoderCmdTblId; +}ASIC_ENCODER_INFO; + +typedef struct _ATOM_DISP_OUT_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT ptrTransmitterInfo; + USHORT ptrEncoderInfo; + ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; + ASIC_ENCODER_INFO asEncoderInfo[1]; +}ATOM_DISP_OUT_INFO; + +// DispDevicePriorityInfo +typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT asDevicePriority[16]; +}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; + +//ProcessAuxChannelTransactionTable +typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS +{ + USHORT lpAuxRequest; + USHORT lpDataOut; + UCHAR ucChannelID; + union + { + UCHAR ucReplyStatus; + UCHAR ucDelay; + }; + UCHAR ucDataOutLen; + UCHAR ucReserved; +}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; + +#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS + +//GetSinkType + +typedef struct _DP_ENCODER_SERVICE_PARAMETERS +{ + USHORT ucLinkClock; + union + { + UCHAR ucConfig; // for DP training command + UCHAR ucI2cId; // use for GET_SINK_TYPE command + }; + UCHAR ucAction; + UCHAR ucStatus; + UCHAR ucLaneNum; + UCHAR ucReserved[2]; +}DP_ENCODER_SERVICE_PARAMETERS; + +// ucAction +#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 +#define ATOM_DP_ACTION_TRAINING_START 0x02 +#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 +#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 +#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 +#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 + +// ucConfig +#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 +#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 +#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 +#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 +#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 +#define ATOM_DP_CONFIG_LINK_A 0x00 +#define ATOM_DP_CONFIG_LINK_B 0x04 + +#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS + +// DP_TRAINING_TABLE +#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR +#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) +#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) +#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) +#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) +#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) +#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) +#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) +#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) +#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) +#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) +#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) + + +/****************************************************************************/ +//Portion VI: Definitinos being oboselete +/****************************************************************************/ + +//========================================================================================== +//Remove the definitions below when driver is ready! +typedef struct _ATOM_DAC_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMaxFrequency; // in 10kHz unit + USHORT usReserved; +}ATOM_DAC_INFO; + + +typedef struct _COMPASSIONATE_DATA +{ + ATOM_COMMON_TABLE_HEADER sHeader; + + //============================== DAC1 portion + UCHAR ucDAC1_BG_Adjustment; + UCHAR ucDAC1_DAC_Adjustment; + USHORT usDAC1_FORCE_Data; + //============================== DAC2 portion + UCHAR ucDAC2_CRT2_BG_Adjustment; + UCHAR ucDAC2_CRT2_DAC_Adjustment; + USHORT usDAC2_CRT2_FORCE_Data; + USHORT usDAC2_CRT2_MUX_RegisterIndex; + UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low + UCHAR ucDAC2_NTSC_BG_Adjustment; + UCHAR ucDAC2_NTSC_DAC_Adjustment; + USHORT usDAC2_TV1_FORCE_Data; + USHORT usDAC2_TV1_MUX_RegisterIndex; + UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low + UCHAR ucDAC2_CV_BG_Adjustment; + UCHAR ucDAC2_CV_DAC_Adjustment; + USHORT usDAC2_CV_FORCE_Data; + USHORT usDAC2_CV_MUX_RegisterIndex; + UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low + UCHAR ucDAC2_PAL_BG_Adjustment; + UCHAR ucDAC2_PAL_DAC_Adjustment; + USHORT usDAC2_TV2_FORCE_Data; +}COMPASSIONATE_DATA; + +/****************************Supported Device Info Table Definitions**********************/ +// ucConnectInfo: +// [7:4] - connector type +// = 1 - VGA connector +// = 2 - DVI-I +// = 3 - DVI-D +// = 4 - DVI-A +// = 5 - SVIDEO +// = 6 - COMPOSITE +// = 7 - LVDS +// = 8 - DIGITAL LINK +// = 9 - SCART +// = 0xA - HDMI_type A +// = 0xB - HDMI_type B +// = 0xE - Special case1 (DVI+DIN) +// Others=TBD +// [3:0] - DAC Associated +// = 0 - no DAC +// = 1 - DACA +// = 2 - DACB +// = 3 - External DAC +// Others=TBD +// + +typedef struct _ATOM_CONNECTOR_INFO +{ + UCHAR bfAssociatedDAC:4; + UCHAR bfConnectorType:4; +}ATOM_CONNECTOR_INFO; + +typedef union _ATOM_CONNECTOR_INFO_ACCESS +{ + ATOM_CONNECTOR_INFO sbfAccess; + UCHAR ucAccess; +}ATOM_CONNECTOR_INFO_ACCESS; + +typedef struct _ATOM_CONNECTOR_INFO_I2C +{ + ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; +}ATOM_CONNECTOR_INFO_I2C; + + +typedef struct _ATOM_SUPPORTED_DEVICES_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; +}ATOM_SUPPORTED_DEVICES_INFO; + +#define NO_INT_SRC_MAPPED 0xFF + +typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP +{ + UCHAR ucIntSrcBitmap; +}ATOM_CONNECTOR_INC_SRC_BITMAP; + +typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; + ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; +}ATOM_SUPPORTED_DEVICES_INFO_2; + +typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDeviceSupport; + ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; + ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; +}ATOM_SUPPORTED_DEVICES_INFO_2d1; + +#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 + + + +typedef struct _ATOM_MISC_CONTROL_INFO +{ + USHORT usFrequency; + UCHAR ucPLL_ChargePump; // PLL charge-pump gain control + UCHAR ucPLL_DutyCycle; // PLL duty cycle control + UCHAR ucPLL_VCO_Gain; // PLL VCO gain control + UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control +}ATOM_MISC_CONTROL_INFO; + + +#define ATOM_MAX_MISC_INFO 4 + +typedef struct _ATOM_TMDS_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usMaxFrequency; // in 10Khz + ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; +}ATOM_TMDS_INFO; + + +typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE +{ + UCHAR ucTVStandard; //Same as TV standards defined above, + UCHAR ucPadding[1]; +}ATOM_ENCODER_ANALOG_ATTRIBUTE; + +typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE +{ + UCHAR ucAttribute; //Same as other digital encoder attributes defined above + UCHAR ucPadding[1]; +}ATOM_ENCODER_DIGITAL_ATTRIBUTE; + +typedef union _ATOM_ENCODER_ATTRIBUTE +{ + ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; + ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; +}ATOM_ENCODER_ATTRIBUTE; + + +typedef struct _DVO_ENCODER_CONTROL_PARAMETERS +{ + USHORT usPixelClock; + USHORT usEncoderID; + UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. + UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT + ATOM_ENCODER_ATTRIBUTE usDevAttr; +}DVO_ENCODER_CONTROL_PARAMETERS; + +typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION +{ + DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; + WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion +}DVO_ENCODER_CONTROL_PS_ALLOCATION; + + +#define ATOM_XTMDS_ASIC_SI164_ID 1 +#define ATOM_XTMDS_ASIC_SI178_ID 2 +#define ATOM_XTMDS_ASIC_TFP513_ID 3 +#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 +#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 +#define ATOM_XTMDS_MVPU_FPGA 0x00000004 + + +typedef struct _ATOM_XTMDS_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usSingleLinkMaxFrequency; + ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip + UCHAR ucXtransimitterID; + UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported + UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters + // due to design. This ID is used to alert driver that the sequence is not "standard"! + UCHAR ucMasterAddress; // Address to control Master xTMDS Chip + UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip +}ATOM_XTMDS_INFO; + +typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS +{ + UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off + UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... + UCHAR ucPadding[2]; +}DFP_DPMS_STATUS_CHANGE_PARAMETERS; + +/****************************Legacy Power Play Table Definitions **********************/ + +//Definitions for ulPowerPlayMiscInfo +#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L +#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L +#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L + +#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L +#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L + +#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L + +#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L +#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L +#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program + +#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L +#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L +#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L +#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L +#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L +#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L +#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L + +#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L +#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L +#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L +#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L +#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L + +#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved +#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 + +#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L +#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L +#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L +#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic +#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic +#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode + +#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) +#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 +#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L + +#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L +#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L +#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L +#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L +#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L +#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L +#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. + //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback +#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L +#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L +#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L + +//ucTableFormatRevision=1 +//ucTableContentRevision=1 +typedef struct _ATOM_POWERMODE_INFO +{ + ULONG ulMiscInfo; //The power level should be arranged in ascending order + ULONG ulReserved1; // must set to 0 + ULONG ulReserved2; // must set to 0 + USHORT usEngineClock; + USHORT usMemoryClock; + UCHAR ucVoltageDropIndex; // index to GPIO table + UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate + UCHAR ucMinTemperature; + UCHAR ucMaxTemperature; + UCHAR ucNumPciELanes; // number of PCIE lanes +}ATOM_POWERMODE_INFO; + +//ucTableFormatRevision=2 +//ucTableContentRevision=1 +typedef struct _ATOM_POWERMODE_INFO_V2 +{ + ULONG ulMiscInfo; //The power level should be arranged in ascending order + ULONG ulMiscInfo2; + ULONG ulEngineClock; + ULONG ulMemoryClock; + UCHAR ucVoltageDropIndex; // index to GPIO table + UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate + UCHAR ucMinTemperature; + UCHAR ucMaxTemperature; + UCHAR ucNumPciELanes; // number of PCIE lanes +}ATOM_POWERMODE_INFO_V2; + +//ucTableFormatRevision=2 +//ucTableContentRevision=2 +typedef struct _ATOM_POWERMODE_INFO_V3 +{ + ULONG ulMiscInfo; //The power level should be arranged in ascending order + ULONG ulMiscInfo2; + ULONG ulEngineClock; + ULONG ulMemoryClock; + UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table + UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate + UCHAR ucMinTemperature; + UCHAR ucMaxTemperature; + UCHAR ucNumPciELanes; // number of PCIE lanes + UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table +}ATOM_POWERMODE_INFO_V3; + + +#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 + +#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 +#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 + +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 +#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog + + +typedef struct _ATOM_POWERPLAY_INFO +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucOverdriveThermalController; + UCHAR ucOverdriveI2cLine; + UCHAR ucOverdriveIntBitmap; + UCHAR ucOverdriveControllerAddress; + UCHAR ucSizeOfPowerModeEntry; + UCHAR ucNumOfPowerModeEntries; + ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +}ATOM_POWERPLAY_INFO; + +typedef struct _ATOM_POWERPLAY_INFO_V2 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucOverdriveThermalController; + UCHAR ucOverdriveI2cLine; + UCHAR ucOverdriveIntBitmap; + UCHAR ucOverdriveControllerAddress; + UCHAR ucSizeOfPowerModeEntry; + UCHAR ucNumOfPowerModeEntries; + ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +}ATOM_POWERPLAY_INFO_V2; + +typedef struct _ATOM_POWERPLAY_INFO_V3 +{ + ATOM_COMMON_TABLE_HEADER sHeader; + UCHAR ucOverdriveThermalController; + UCHAR ucOverdriveI2cLine; + UCHAR ucOverdriveIntBitmap; + UCHAR ucOverdriveControllerAddress; + UCHAR ucSizeOfPowerModeEntry; + UCHAR ucNumOfPowerModeEntries; + ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +}ATOM_POWERPLAY_INFO_V3; + + + +/**************************************************************************/ + + +// Following definitions are for compatiblity issue in different SW components. +#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 +#define Object_Info Object_Header +#define AdjustARB_SEQ MC_InitParameter +#define VRAM_GPIO_DetectionInfo VoltageObjectInfo +#define ASIC_VDDCI_Info ASIC_ProfilingInfo +#define ASIC_MVDDQ_Info MemoryTrainingInfo +#define SS_Info PPLL_SS_Info +#define ASIC_MVDDC_Info ASIC_InternalSS_Info +#define DispDevicePriorityInfo SaveRestoreInfo +#define DispOutInfo TV_VideoMode + + +#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE +#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE + +#define ATOM_S3_SCALER2_ACTIVE_H 0x00004000L +#define ATOM_S3_SCALER2_ACTIVE_V 0x00008000L +#define ATOM_S6_REQ_SCALER2_H 0x00004000L +#define ATOM_S6_REQ_SCALER2_V 0x00008000L + +#define ATOM_S3_SCALER1_ACTIVE_H 0x00001000L +#define ATOM_S3_SCALER1_ACTIVE_V 0x00002000L + +#define ATOM_S6_REQ_SCALER1_H ATOM_S6_REQ_LCD_EXPANSION_FULL +#define ATOM_S6_REQ_SCALER1_V ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO + +//New device naming, remove them when both DAL/VBIOS is ready +#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS +#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS + +#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS +#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS + +#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS +#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION + +#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT +#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT + +#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX +#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX + +#define ATOM_DEVICE_DFP2I_INDEX 0x00000009 +#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) + +#define ATOM_S0_DFP1I ATOM_S0_DFP1 +#define ATOM_S0_DFP1X ATOM_S0_DFP2 + +#define ATOM_S0_DFP2I 0x00200000L +#define ATOM_S0_DFP2Ib2 0x20 + +#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE +#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE + +#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L +#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 + +#define ATOM_S3_DFP2I_ACTIVEb1 0x02 + +#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE +#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE + +#define ATOM_S3_DFP2I_ACTIVE 0x00000200L + +#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE +#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE +#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L + +#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 +#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 + +#define ATOM_S5_DOS_REQ_DFP2I 0x0200 +#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 +#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 + +#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 +#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L + +#define TMDS1XEncoderControl DVOEncoderControl +#define DFP1XOutputControl DVOOutputControl + +#define ExternalDFPOutputControl DFP1XOutputControl +#define EnableExternalTMDS_Encoder TMDS1XEncoderControl + +#define DFP1IOutputControl TMDSAOutputControl +#define DFP2IOutputControl LVTMAOutputControl + +#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS +#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION + +#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS +#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION + +#define ucDac1Standard ucDacStandard +#define ucDac2Standard ucDacStandard + +#define TMDS1EncoderControl TMDSAEncoderControl +#define TMDS2EncoderControl LVTMAEncoderControl + +#define DFP1OutputControl TMDSAOutputControl +#define DFP2OutputControl LVTMAOutputControl +#define CRT1OutputControl DAC1OutputControl +#define CRT2OutputControl DAC2OutputControl + +//These two lines will be removed for sure in a few days, will follow up with Michael V. +#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL +#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL + +/*********************************************************************************/ + +//========================================================================================== + +#pragma pack() // BIOS data must use byte aligment + +#endif /* _ATOMBIOS_H */ diff --git a/src/AtomBios/includes/regsdef.h b/src/AtomBios/includes/regsdef.h new file mode 100644 index 00000000..e557ac04 --- /dev/null +++ b/src/AtomBios/includes/regsdef.h @@ -0,0 +1,25 @@ +/* + * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +//This is a dummy file used by driver-parser during compilation. +//Without this file, compatibility will be broken among ASICs and BIOs vs. driver +//James H. Apr. 22/03 diff --git a/src/Makefile.am b/src/Makefile.am index ff1e2253..bcc66373 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -32,6 +32,20 @@ R128_DRI_SRCS = r128_dri.c RADEON_DRI_SRCS = radeon_dri.c endif +RADEON_ATOMBIOS_SOURCES = AtomBios/CD_Operations.c\ + AtomBios/Decoder.c\ + AtomBios/hwserv_drv.c \ + AtomBios/includes/atombios.h \ + AtomBios/includes/CD_binding.h \ + AtomBios/includes/CD_Common_Types.h \ + AtomBios/includes/CD_Definitions.h \ + AtomBios/includes/CD_hw_services.h \ + AtomBios/includes/CD_Opcodes.h \ + AtomBios/includes/CD_Structs.h \ + AtomBios/includes/Decoder.h \ + AtomBios/includes/regsdef.h + + if ATIMISC_CPIO ATIMISC_CPIO_SOURCES = ativga.c ativgaio.c atibank.c atiwonder.c atiwonderio.c endif @@ -45,7 +59,8 @@ ATIMISC_EXA_SOURCES = atimach64exa.c RADEON_EXA_SOURCES = radeon_exa.c endif -AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ +AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER +INCLUDES = -I$(srcdir)/AtomBios/includes ati_drv_la_LTLIBRARIES = ati_drv.la ati_drv_la_LDFLAGS = -module -avoid-version @@ -85,7 +100,8 @@ radeon_drv_la_SOURCES = \ radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \ radeon_vip.c radeon_misc.c radeon_probe.c radeon_display.c \ radeon_crtc.c radeon_output.c radeon_modes.c radeon_tv.c \ - $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) + $(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c\ + $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c theatre_detect_drv_la_LTLIBRARIES = theatre_detect_drv.la theatre_detect_drv_la_LDFLAGS = -module -avoid-version diff --git a/src/avivo_reg.h b/src/avivo_reg.h new file mode 100644 index 00000000..f2bdc968 --- /dev/null +++ b/src/avivo_reg.h @@ -0,0 +1,503 @@ +/* AVIVO registers are specific to the AVIVO display engine, first + * introduced on R5xx. + * + * CRTCs are the master unit. A CRTC controls scanout, and both the + * DACs (be it TV or VGA) and TMDS transmitters take their input from + * the CRTC. + */ +#define IS_AVIVO_VARIANT 1 + +/* Core engine. */ +#define AVIVO_ENGINE_STATUS 0x0014 + +/* Memory mapping. */ +#define AVIVO_MC_INDEX 0x0070 +/* AVIVO_MC_MEMORY_MAP control memory mapping of the video card ram: + * base is higher 16bits of the starting address at which card + * sees it own memory. end is higher 16bits address at which card + * memory should end (might be usefull if you want to use half memory + * but don't know what does the card if you address out of bound + * memory, likely trigger pci stuff which often end in bad things). + */ +# define MC00 0x00 +#define R520_MC_STATUS 0x00 +#define R520_MC_STATUS_IDLE (1<<1) +# define MC01 0x01 +# define MC02 0x02 +# define MC03 0x03 +# define AVIVO_MC_MEMORY_MAP 0x04 +# define AVIVO_MC_MEMORY_MAP_BASE_MASK (0xFFFF << 0) +# define AVIVO_MC_MEMORY_MAP_BASE_SHIFT 0 +# define AVIVO_MC_MEMORY_MAP_END_MASK (0xFFFF << 16) +# define AVIVO_MC_MEMORY_MAP_END_SHIFT 16 +# define MC05 0x05 +# define MC06 0x06 +# define MC07 0x07 +# define MC08 0x08 +#define RV515_MC_STATUS 0x08 +#define RV515_MC_STATUS_IDLE (1<<4) +# define MC09 0x09 +# define MC0a 0x0a +# define MC0b 0x0b +# define MC0c 0x0c +# define MC0d 0x0d +# define MC0e 0x0e +# define MC0f 0x0f +# define MC10 0x10 +# define MC11 0x11 +# define MC12 0x12 +# define MC13 0x13 +# define MC14 0x14 +# define MC15 0x15 +# define MC16 0x16 +# define MC17 0x17 +# define MC18 0x18 +# define MC19 0x19 +# define MC1a 0x1a +# define MC1b 0x1b +# define MC1c 0x1c +# define MC1d 0x1d +# define MC1e 0x1e +# define MC1f 0x1f +#define AVIVO_MC_DATA 0x0074 + +/* + * You set memory base at which card see its memory (should be the + * same as AVIVO_MC_MEMORY_MAP lower 16bits + */ +#define AVIVO_VGA_MEMORY_BASE 0x0134 +#define AVIVO_VGA_FB_START 0x0310 +#define AVIVO_VGA1_CONTROL 0x0330 + #define AVIVO_VGA1_CONTROL_MODE_ENABLE (1<<0) + #define AVIVO_VGA1_CONTROL_TIMING_SELECT (1<<8) + #define AVIVO_VGA1_CONTROL_SYNC_POLARITY_SELECT (1<<9) + #define AVIVO_VGA1_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) + #define AVIVO_VGA1_CONTROL_OVERSCAN_COLOR_EN (1<<16) + #define AVIVO_VGA1_CONTROL_ROTATE (1<<24) +#define AVIVO_VGA2_CONTROL 0x0338 + #define AVIVO_VGA2_CONTROL_MODE_ENABLE (1<<0) + #define AVIVO_VGA2_CONTROL_TIMING_SELECT (1<<8) + #define AVIVO_VGA2_CONTROL_SYNC_POLARITY_SELECT (1<<9) + #define AVIVO_VGA2_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) + #define AVIVO_VGA2_CONTROL_OVERSCAN_COLOR_EN (1<<16) + #define AVIVO_VGA2_CONTROL_ROTATE (1<<24) + +/* + * We believe reference clock is 108Mhz, we likely can change that using + * mystery PLL reg spoted below more dump are needed in order to find out. + * + * The formula we derived so far seems to work for card we have: + * (vclk is video mode clock) + * vclk = (1080 * AVIVO_PLL_POST_MUL) / + * (AVIVO_PLL_DIVIDER * AVIVO_PLL_POST_DIV * 40) + * It seems that AVIVO_PLL_DIVIDER * AVIVO_PLL_POST_DIV needs to be + * above 40 and that AVIVO_DIVIDER should be greater than AVIVO_PLL_POST_DIV + * Try to keep this constraint while computing PLL values. + */ +#define AVIVO_PLL1_POST_DIV_CNTL 0x0400 // REF_DIV_SRC +# define AVIVO_PLL_POST_DIV_EN (1 << 0) +#define AVIVO_PLL1_POST_DIV 0x0404 // REF_DIV +#define AVIVO_PLL1_POST_DIV_MYSTERY 0x040C +# define AVIVO_PLL_POST_DIV_MYSTERY_VALUE 0x10000 +#define AVIVO_PLL2_POST_DIV_CNTL 0x0410 +#define AVIVO_PLL2_POST_DIV 0x0414 +#define AVIVO_PLL2_POST_DIV_MYSTERY 0x041C +#define AVIVO_PLL1_POST_MUL 0x0430 // FB_DIV +# define AVIVO_PLL_POST_MUL_SHIFT 16 +#define AVIVO_PLL2_POST_MUL 0x0434 // FB_DIV +#define AVIVO_PLL1_DIVIDER_CNTL 0x0438 // POST DIV_SRC +# define AVIVO_PLL_DIVIDER_EN (1 << 0) +#define AVIVO_PLL1_DIVIDER 0x043C // POST DIV +#define AVIVO_PLL2_DIVIDER_CNTL 0x0440 +#define AVIVO_PLL2_DIVIDER 0x0444 // POST_DIV +#define AVIVO_PLL1_MYSTERY0 0x0448 // POST_DIV_SRC +# define AVIVO_PLL_MYSTERY0_VALUE 0x20704 +#define AVIVO_PLL2_MYSTERY0 0x044C +#define AVIVO_PLL1_MYSTERY1 0x0450 +# define AVIVO_PLL_MYSTERY1_VALUE 0x4310000 +#define AVIVO_PLL2_MYSTERY1 0x0454 +#define AVIVO_CRTC_PLL_SOURCE 0x0484 +# define AVIVO_CRTC1_PLL_SOURCE_SHIFT 0 +# define AVIVO_CRTC2_PLL_SOURCE_SHIFT 16 + +/* CRTC controls; these appear to influence the DAC's scanout. */ +#define AVIVO_CRTC1_H_TOTAL 0x6000 +#define AVIVO_CRTC1_H_BLANK 0x6004 +#define AVIVO_CRTC1_H_SYNC_WID 0x6008 +#define AVIVO_CRTC1_H_SYNC_POL 0x600c +#define AVIVO_CRTC1_V_TOTAL 0x6020 +#define AVIVO_CRTC1_V_BLANK 0x6024 +#define AVIVO_CRTC1_V_SYNC_WID 0x6028 +#define AVIVO_CRTC1_V_SYNC_POL 0x602c +#define AVIVO_CRTC1_CNTL 0x6080 +# define AVIVO_CRTC_EN (1 << 0) +#define AVIVO_CRTC1_BLANK_STATUS 0x6084 +#define AVIVO_CRTC1_STEREO_STATUS 0x60c0 + +/* These all appear to control the scanout from the framebuffer. + * Flicking SCAN_ENABLE low results in a black screen -- aside from + * the cursor. Messing with PITCH gives you the obvious symptoms, + * and messing with X_LENGTH and Y_LENGTH will give you a black + * screen beyond those bounds if you make it shorter. + * + * Messing with the format gives you ... odd results. Setting it + * to 3 exactly quadruples my display size, with the next three + * panes displaying the next parts of FB memory. BPP? + * + * FB_LOCATION gives me the obvious result; FB_END is exactly + * FB_LOCATION + (xres * yres * 2). FB_END doesn't appear to actually + * function as an upper bound. + */ +#define AVIVO_CRTC1_SCAN_ENABLE 0x6100 +# define AVIVO_CRTC_SCAN_EN (1 << 0) +#define AVIVO_CRTC1_FB_FORMAT 0x6104 +# define AVIVO_CRTC_FORMAT_ARGB15 (1 << 0) +# define AVIVO_CRTC_FORMAT_ARGB16 ((1 << 0) | (1 << 8)) +# define AVIVO_CRTC_FORMAT_ARGB32 (1 << 1) +# define AVIVO_CRTC_TILED (1 << 20) +# define AVIVO_CRTC_MACRO_ADDRESS_MODE (1 << 21) +#define AVIVO_CRTC1_FB_LOCATION 0x6110 +#define AVIVO_CRTC1_FB_END 0x6118 +/* This is in pixels, not bytes. Obviously. */ +#define AVIVO_CRTC1_PITCH 0x6120 +#define AVIVO_CRTC1_X_LENGTH 0x6134 +#define AVIVO_CRTC1_Y_LENGTH 0x6138 + +#define AVIVO_CRTC1_OFFSET_END 0x6454 + +#define AVIVO_CRTC1_FB_HEIGHT 0x652c +#define AVIVO_CRTC1_OFFSET_START 0x6580 +#define AVIVO_CRTC1_EXPANSION_SOURCE 0x6584 +#define AVIVO_CRTC1_EXPANSION_CNTL 0x6590 +# define AVIVO_CRTC_EXPANSION_EN (1 << 0) +#define AVIVO_CRTC1_6594 0x6594 +# define AVIVO_CRTC1_6594_VALUE ((1 << 8) | (1 << 0)) +#define AVIVO_CRTC1_659C 0x659C +# define AVIVO_CRTC1_659C_VALUE ((1 << 1)) +#define AVIVO_CRTC1_65A4 0x65a4 +# define AVIVO_CRTC1_65A4_VALUE ((1 << 16) | (1 << 0)) +#define AVIVO_CRTC1_65A8 0x65a8 +# define AVIVO_CRTC1_65A8_VALUE ((1 << 16) | (1 << 14)) +#define AVIVO_CRTC1_65AC 0x65ac +# define AVIVO_CRTC1_65AC_VALUE ((1 << 15) | (1 << 14) | (1 << 13)) +#define AVIVO_CRTC1_65B0 0x65b0 +# define AVIVO_CRTC1_65B0_VALUE ((1 << 17) | (1 << 16) | (1 << 8)) +#define AVIVO_CRTC1_65B8 0x65b8 +# define AVIVO_CRTC1_65B8_VALUE ((1 << 16)) +#define AVIVO_CRTC1_65BC 0x65bc +# define AVIVO_CRTC1_65BC_VALUE ((1 << 16)) +#define AVIVO_CRTC1_65C0 0x65c0 +# define AVIVO_CRTC1_65C0_VALUE ((1 << 17) | (1 << 16) | (1 << 8)) +#define AVIVO_CRTC1_65C8 0x65c8 +# define AVIVO_CRTC1_65C8_VALUE ((1 << 16)) + +#define AVIVO_CRTC2_H_TOTAL 0x6800 +#define AVIVO_CRTC2_H_BLANK 0x6804 +#define AVIVO_CRTC2_H_SYNC_WID 0x6808 +#define AVIVO_CRTC2_H_SYNC_POL 0x680c +#define AVIVO_CRTC2_V_TOTAL 0x6820 +#define AVIVO_CRTC2_V_BLANK 0x6824 +#define AVIVO_CRTC2_V_SYNC_WID 0x6828 +#define AVIVO_CRTC2_V_SYNC_POL 0x682c +#define AVIVO_CRTC2_CNTL 0x6880 +#define AVIVO_CRTC2_BLANK_STATUS 0x6884 + +#define AVIVO_CRTC2_SCAN_ENABLE 0x6900 +#define AVIVO_CRTC2_FB_FORMAT 0x6904 +#define AVIVO_CRTC2_FB_LOCATION 0x6910 +#define AVIVO_CRTC2_FB_END 0x6918 +#define AVIVO_CRTC2_PITCH 0x6920 +#define AVIVO_CRTC2_X_LENGTH 0x6934 +#define AVIVO_CRTC2_Y_LENGTH 0x6938 + +#define AVIVO_CRTC2_OFFSET_END 0x6c54 + +#define AVIVO_CRTC2_FB_HEIGHT 0x6d2c +#define AVIVO_CRTC2_OFFSET_START 0x6d80 +#define AVIVO_CRTC2_EXPANSION_SOURCE 0x6d84 +#define AVIVO_CRTC2_EXPANSION_CNTL 0x6d90 +#define AVIVO_CRTC2_6594 0x6d94 +#define AVIVO_CRTC2_659C 0x6d9C +#define AVIVO_CRTC2_65A4 0x6da4 +#define AVIVO_CRTC2_65A8 0x6da8 +#define AVIVO_CRTC2_65AC 0x6dac +#define AVIVO_CRTC2_65B0 0x6db0 +#define AVIVO_CRTC2_65B8 0x6db8 +#define AVIVO_CRTC2_65BC 0x6dbc +#define AVIVO_CRTC2_65C0 0x6dc0 +#define AVIVO_CRTC2_65C8 0x6dc8 + +#define AVIVO_DACA_CNTL 0x7800 +#define AVIVO_DACA_CRTC_SOURCE 0x7804 +# define AVIVO_DAC_EN (1 << 0) +#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) +#define AVIVO_DACA_POWERDOWN 0x7850 +# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) +# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) +# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) +# define AVIVO_DACA_POWERDOWN_RED (1 << 24) + +#define AVIVO_DACB_CNTL 0x7a00 +#define AVIVO_DACB_CRTC_SOURCE 0x7a04 +#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) +#define AVIVO_DACB_POWERDOWN 0x7a50 +# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) +# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) +# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) +# define AVIVO_DACB_POWERDOWN_RED (1 << 24) + +/* Frustratingly, at least on my R580, the DAC and TMDS orders + * appear inversed: 7800 and 7a80 enable/disable the same physical + * connector; ditto 7a00 and 7880. O brave new world! + */ +/* TMDS_CNTL only lower bit of each half bytes matters. + * UNK0 seems to have no effect on LVDS but kill the feed of DVI connector + * UNK1 really unknow: so far no visible change from setting it or not + * UNK2 really unknow: so far no visible change from setting it or not + * UNK3 really unknow: so far no visible change from setting it or not + * UNK4 seems to switch red & blue encoding + * UNK5 is the fun bits on some card people will see their desktop + * tiled 4 times but for most cards this will give wrong pictures + * UNK6 seems to kill the feed LVDS & DVI + */ +#define AVIVO_TMDSA_CNTL 0x7880 +# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) +# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) +# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) +# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) +# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) +# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) +# define AVIVO_TMDSA_CNTL_SWAP (1 << 28) +#define AVIVO_TMDSA_CRTC_SOURCE 0x7884 +/* 78a8 appears to be some kind of (reasonably tolerant) clock? + * 78d0 definitely hits the transmitter, definitely clock. */ +/* MYSTERY1 This appears to control dithering? */ +#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) +#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 +# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) +#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 +# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) +# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) +#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 +#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) + +/* I don't know any of the bits here, only that enabling (1 << 5) + * without (1 << 4) makes things go utterly mental ... seems to be + * the transmitter clock again. */ +/* 790c is a clock? + * 7910 appears to be some kind of control field, again. (1 << 25) + * must be enabled to get a signal on my monitor. */ +#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) + +#define AVIVO_LVTMA_CNTL 0x7a80 +# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) +# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) +# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) +# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) +# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) +# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) +# define AVIVO_LVTMA_CNTL_SWAP (1 << 28) +#define AVIVO_LVTMA_CRTC_SOURCE 0x7a84 +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) + +#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 +# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) + +#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 +# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) +# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) +#define AVIVO_LVTMA_CLOCK_ENABLE 0x7b00 + +#define AVIVO_LVTMA_TRANSMITTER_ENABLE 0x7b04 +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) + +#define AVIVO_LVTMA_TRANSMITTER_CONTROL 0x7b10 +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) + +#define AVIVO_LVTMA_PWRSEQ_CNTL 0x7af0 +# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) +# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) +# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) +# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) +# define AVIVO_LVTMA_SYNCEN (1 << 8) +# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) +# define AVIVO_LVTMA_SYNCEN_POL (1 << 10) +# define AVIVO_LVTMA_DIGON (1 << 16) +# define AVIVO_LVTMA_DIGON_OVRD (1 << 17) +# define AVIVO_LVTMA_DIGON_POL (1 << 18) +# define AVIVO_LVTMA_BLON (1 << 24) +# define AVIVO_LVTMA_BLON_OVRD (1 << 25) +# define AVIVO_LVTMA_BLON_POL (1 << 26) + +#define AVIVO_LVTMA_PWRSEQ_STATE 0x7af4 +# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) +# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) +# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) +# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) +# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) +# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) + +#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 +# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) +# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 +# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 + +/* The BIOS says so, anyway ... */ +#define AVIVO_GPIO_0 0x7e30 +#define AVIVO_GPIO_1 0x7e40 +#define AVIVO_GPIO_2 0x7e50 +#define AVIVO_GPIO_3 0x7e60 + +#define AVIVO_TMDS_STATUS 0x7e9c +# define AVIVO_TMDSA_CONNECTED (1 << 0) +# define AVIVO_LVTMA_CONNECTED (1 << 8) + +/* Cursor registers. */ +#define AVIVO_CURSOR1_CNTL 0x6400 +# define AVIVO_CURSOR_EN (1 << 0) +# define AVIVO_CURSOR_FORMAT_MASK (3 << 8) +# define AVIVO_CURSOR_FORMAT_ABGR 0x1 +# define AVIVO_CURSOR_FORMAT_ARGB 0x2 +# define AVIVO_CURSOR_FORMAT_SHIFT 8 +#define AVIVO_CURSOR1_LOCATION 0x6408 +/* x is in the top 16 bits; y in the lower 16. Note that _SIZE does not + * impact the in-memory format: it is always 64x64. */ +#define AVIVO_CURSOR1_SIZE 0x6410 +#define AVIVO_CURSOR1_POSITION 0x6414 + +#define AVIVO_I2C_STATUS 0x7d30 +# define AVIVO_I2C_STATUS_DONE (1 << 0) +# define AVIVO_I2C_STATUS_NACK (1 << 1) +# define AVIVO_I2C_STATUS_HALT (1 << 2) +# define AVIVO_I2C_STATUS_GO (1 << 3) +# define AVIVO_I2C_STATUS_MASK 0x7 +/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe + * DONE? */ +# define AVIVO_I2C_STATUS_CMD_RESET 0x7 +# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) +#define AVIVO_I2C_STOP 0x7d34 +#define AVIVO_I2C_START_CNTL 0x7d38 +# define AVIVO_I2C_START (1 << 8) +# define AVIVO_I2C_CONNECTOR0 (0 << 16) +# define AVIVO_I2C_CONNECTOR1 (1 << 16) +#define R520_I2C_START (1<<0) +#define R520_I2C_STOP (1<<1) +#define R520_I2C_RX (1<<2) +#define R520_I2C_EN (1<<8) +#define R520_I2C_DDC1 (0<<16) +#define R520_I2C_DDC2 (1<<16) +#define R520_I2C_DDC3 (2<<16) +#define R520_I2C_DDC_MASK (3<<16) +#define AVIVO_I2C_CONTROL2 0x7d3c +# define AVIVO_I2C_7D3C_SIZE_SHIFT 8 +# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) +#define AVIVO_I2C_CONTROL3 0x7d40 +/* Reading is done 4 bytes at a time: read the bottom 8 bits from + * 7d44, four times in a row. + * Writing is a little more complex. First write DATA with + * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic + * magic number, zz is, I think, the slave address, and yy is the byte + * you want to write. */ +#define AVIVO_I2C_DATA 0x7d44 +#define R520_I2C_ADDR_COUNT_MASK (0x7) +#define R520_I2C_DATA_COUNT_SHIFT (8) +#define R520_I2C_DATA_COUNT_MASK (0xF00) +#define AVIVO_I2C_CNTL 0x7d50 +# define AVIVO_I2C_EN (1 << 0) +# define AVIVO_I2C_RESET (1 << 8) + + +#define R520_PCLK_HDCP_CNTL 0x494 + +#define AVIVO_HDP_FB_LOCATION 0x134 +#define AVIVO_VGA_MEM_BASE 0x310 +#define AVIVO_VGA_SURF_ADDR 0x318 +#define AVIVO_D1VGA_CTRL 0x330 +#define AVIVO_D2VGA_CTRL 0x338 + +#define AVIVO_DVGA_MODE_ENABLE (1<<0) + + diff --git a/src/radeon.h b/src/radeon.h index 532f04c1..1d2235c2 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -443,6 +443,8 @@ typedef enum { CARD_PCIE } RADEONCardType; +typedef struct _atomBIOSHandle *atomBIOSHandlePtr; + typedef struct { EntityInfoPtr pEnt; pciVideoPtr PciInfo; @@ -817,6 +819,15 @@ typedef struct { RADEONMacModel MacModel; #endif + atomBIOSHandlePtr atomBIOS; + unsigned long FbFreeStart, FbFreeSize; + + int cursor_width; + int cursor_height; + int cursor_format; + int cursor_x; + int cursor_y; + Rotation rotation; void (*PointerMoved)(int, int, int); CreateScreenResourcesProcPtr CreateScreenResources; diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c new file mode 100644 index 00000000..12af4eb4 --- /dev/null +++ b/src/radeon_atombios.c @@ -0,0 +1,1104 @@ +/* + * Copyright 2007 Egbert Eich <eich@novell.com> + * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Matthias Hopf <mhopf@novell.com> + * Copyright 2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifdef HAVE_CONFIG_H +# include "config.h" +#endif +#include "xf86.h" +#include "xf86_OSproc.h" +#include "radeon.h" +#include "radeon_atombios.h" +#include "radeon_macros.h" + +#include "xorg-server.h" +#if XSERVER_LIBPCIACCESS +#warning pciaccess defined +#endif + +char *AtomBIOSQueryStr[] = { + "Default Engine Clock", + "Default Memory Clock", + "Maximum Pixel ClockPLL Frequency Output", + "Minimum Pixel ClockPLL Frequency Output", + "Maximum Pixel ClockPLL Frequency Input", + "Minimum Pixel ClockPLL Frequency Input", + "Minimum Pixel Clock", + "Reference Clock", + "Start of VRAM area used by Firmware", + "Framebuffer space used by Firmware (kb)", + "TDMS Frequency", + "PLL ChargePump", + "PLL DutyCycle", + "PLL VCO Gain", + "PLL VoltageSwing" +}; + +char *AtomBIOSFuncStr[] = { + "AtomBIOS Init", + "AtomBIOS Teardown", + "AtomBIOS Exec", + "AtomBIOS Set FB Space" +}; + +#define DEBUGP(x) {x;} +#define LOG_DEBUG 7 + +#ifdef ATOM_BIOS +# define LOG_CAIL LOG_DEBUG + 1 + +#ifdef ATOM_BIOS_PARSER +static void +CailDebug(int scrnIndex, const char *format, ...) +{ + va_list ap; + + va_start(ap, format); + xf86VDrvMsgVerb(scrnIndex, X_INFO, LOG_CAIL, format, ap); + va_end(ap); +} +#endif + +# define CAILFUNC(ptr) \ + CailDebug(((atomBIOSHandlePtr)(ptr))->scrnIndex, "CAIL: %s\n", __func__) + + +enum { + legacyBIOSLocation = 0xC0000, + legacyBIOSMax = 0x10000 +}; + +static int +rhdAnalyzeCommonHdr(ATOM_COMMON_TABLE_HEADER *hdr) +{ + if (hdr->usStructureSize == 0xaa55) + return FALSE; + + return TRUE; +} + +static int +rhdAnalyzeRomHdr(unsigned char *rombase, + ATOM_ROM_HEADER *hdr, + int *data_offset, int *command_offset) +{ + if (rhdAnalyzeCommonHdr(&hdr->sHeader) == -1) { + return FALSE; + } + xf86ErrorF("\tSubsysemVendorID: 0x%4.4x SubsystemID: 0x%4.4x\n", + hdr->usSubsystemVendorID,hdr->usSubsystemID); + xf86ErrorF("\tIOBaseAddress: 0x%4.4x\n",hdr->usIoBaseAddress); + xf86ErrorFVerb(3,"\tFilename: %s\n",rombase + hdr->usConfigFilenameOffset); + xf86ErrorFVerb(3,"\tBIOS Bootup Message: %s\n", + rombase + hdr->usBIOS_BootupMessageOffset); + + *data_offset = hdr->usMasterDataTableOffset; + *command_offset = hdr->usMasterCommandTableOffset; + + return TRUE; +} + +static int +rhdAnalyzeRomDataTable(unsigned char *base, int offset, + void *ptr,short *size) +{ + ATOM_COMMON_TABLE_HEADER *table = (ATOM_COMMON_TABLE_HEADER *) + (base + offset); + + if (!*size || rhdAnalyzeCommonHdr(table) == -1) { + if (*size) *size -= 2; + *(void **)ptr = NULL; + return FALSE; + } + *size -= 2; + *(void **)ptr = (void *)(table); + return TRUE; +} + +static Bool +rhdGetAtomBiosTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr, + CARD8 *contentRev, + CARD8 *formatRev, + short *size) +{ + if (!hdr) + return FALSE; + + if (contentRev) *contentRev = hdr->ucTableContentRevision; + if (formatRev) *formatRev = hdr->ucTableFormatRevision; + if (size) *size = (short)hdr->usStructureSize + - sizeof(ATOM_COMMON_TABLE_HEADER); + return TRUE; +} + +static Bool +rhdAnalyzeMasterDataTable(unsigned char *base, + ATOM_MASTER_DATA_TABLE *table, + atomDataTablesPtr data) +{ + ATOM_MASTER_LIST_OF_DATA_TABLES *data_table = + &table->ListOfDataTables; + short size; + + if (!rhdAnalyzeCommonHdr(&table->sHeader)) + return FALSE; + if (!rhdGetAtomBiosTableRevisionAndSize(&table->sHeader,NULL,NULL,&size)) + return FALSE; +# define SET_DATA_TABLE(x) {\ + rhdAnalyzeRomDataTable(base,data_table->x,(void *)(&(data->x)),&size); \ + } + +# define SET_DATA_TABLE_VERS(x) {\ + rhdAnalyzeRomDataTable(base,data_table->x,&(data->x.base),&size); \ + } + + SET_DATA_TABLE(UtilityPipeLine); + SET_DATA_TABLE(MultimediaCapabilityInfo); + SET_DATA_TABLE(MultimediaConfigInfo); + SET_DATA_TABLE(StandardVESA_Timing); + SET_DATA_TABLE_VERS(FirmwareInfo); + SET_DATA_TABLE(DAC_Info); + SET_DATA_TABLE_VERS(LVDS_Info); + SET_DATA_TABLE(TMDS_Info); + SET_DATA_TABLE(AnalogTV_Info); + SET_DATA_TABLE_VERS(SupportedDevicesInfo); + SET_DATA_TABLE(GPIO_I2C_Info); + SET_DATA_TABLE(VRAM_UsageByFirmware); + SET_DATA_TABLE(GPIO_Pin_LUT); + SET_DATA_TABLE(VESA_ToInternalModeLUT); + SET_DATA_TABLE_VERS(ComponentVideoInfo); + SET_DATA_TABLE(PowerPlayInfo); + SET_DATA_TABLE(CompassionateData); + SET_DATA_TABLE(SaveRestoreInfo); + SET_DATA_TABLE(PPLL_SS_Info); + SET_DATA_TABLE(OemInfo); + SET_DATA_TABLE(XTMDS_Info); + SET_DATA_TABLE(MclkSS_Info); + SET_DATA_TABLE(Object_Header); + SET_DATA_TABLE(IndirectIOAccess); + SET_DATA_TABLE(MC_InitParameter); + SET_DATA_TABLE(ASIC_VDDC_Info); + SET_DATA_TABLE(ASIC_InternalSS_Info); + SET_DATA_TABLE(TV_VideoMode); + SET_DATA_TABLE_VERS(VRAM_Info); + SET_DATA_TABLE(MemoryTrainingInfo); + SET_DATA_TABLE_VERS(IntegratedSystemInfo); + SET_DATA_TABLE(ASIC_ProfilingInfo); + SET_DATA_TABLE(VoltageObjectInfo); + SET_DATA_TABLE(PowerSourceInfo); +# undef SET_DATA_TABLE + + return TRUE; +} + +Bool +rhdGetAtombiosDataTable(int scrnIndex, unsigned char *base, int *cmd_offset, + atomDataTables *atomDataPtr) +{ + int data_offset; + unsigned short atom_romhdr_off = *(unsigned short*) + (base + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER); + ATOM_ROM_HEADER *atom_rom_hdr = + (ATOM_ROM_HEADER *)(base + atom_romhdr_off); + + // RHDFUNCI(scrnIndex) + + if (memcmp("ATOM",&atom_rom_hdr->uaFirmWareSignature,4)) { + xf86DrvMsg(scrnIndex,X_ERROR,"No AtomBios signature found\n"); + return FALSE; + } + xf86DrvMsg(scrnIndex, X_INFO, "ATOM BIOS Rom: \n"); + if (!rhdAnalyzeRomHdr(base, atom_rom_hdr, &data_offset, cmd_offset)) { + xf86DrvMsg(scrnIndex, X_ERROR, "RomHeader invalid\n"); + return FALSE; + } + if (!rhdAnalyzeMasterDataTable(base, (ATOM_MASTER_DATA_TABLE *) + (base + data_offset), + atomDataPtr)) { + xf86DrvMsg(scrnIndex, X_ERROR, "ROM Master Table invalid\n"); + return FALSE; + } + return TRUE; +} + +static Bool +rhdBIOSGetFbBaseAndSize(int scrnIndex, atomBIOSHandlePtr handle, unsigned int *base, unsigned int *size) +{ + AtomBIOSArg data; + if (RHDAtomBIOSFunc(scrnIndex, handle, GET_FW_FB_SIZE, &data) + == ATOM_SUCCESS) { + if (data.val == 0) { + xf86DrvMsg(scrnIndex, X_WARNING, "%s: AtomBIOS specified VRAM " + "scratch space size invalid\n", __func__); + return FALSE; + } + *size = (int)data.val; + } else + return FALSE; + if (RHDAtomBIOSFunc(scrnIndex, handle, GET_FW_FB_START, &data) + == ATOM_SUCCESS) { + if (data.val == 0) + return FALSE; + *base = (int)data.val; + } + return TRUE; +} + +/* + * Uses videoRam form ScrnInfoRec. + */ +static Bool +rhdAtomBIOSAllocateFbScratch(int scrnIndex, atomBIOSHandlePtr handle, + unsigned *start, unsigned int *size) +{ + unsigned int fb_base = 0; + unsigned int fb_size = 0; + handle->scratchBase = NULL; + handle->fbBase = 0; + + if (rhdBIOSGetFbBaseAndSize(scrnIndex, handle, &fb_base, &fb_size)) { + xf86DrvMsg(scrnIndex, X_INFO, "AtomBIOS requests %ikB" + " of VRAM scratch space\n",fb_size); + fb_size *= 1024; /* convert to bytes */ + xf86DrvMsg(scrnIndex, X_INFO, "AtomBIOS VRAM scratch base: 0x%x\n", + fb_base); + } else { + fb_size = 20 * 1024; + xf86DrvMsg(scrnIndex, X_INFO, " default to: %i\n",fb_size); + } + if (fb_base && fb_size && *size) { + /* 4k align */ + fb_size = (fb_size & ~(CARD32)0xfff) + ((fb_size & 0xfff) ? 1 : 0); + if ((fb_base + fb_size) > (*start + *size)) { + xf86DrvMsg(scrnIndex, X_WARNING, + "%s: FW FB scratch area %i (size: %i)" + " extends beyond available framebuffer size %i\n", + __func__, fb_base, fb_size, *size); + } else if ((fb_base + fb_size) < (*start + *size)) { + xf86DrvMsg(scrnIndex, X_WARNING, + "%s: FW FB scratch area not located " + "at the end of VRAM. Scratch End: " + "0x%x VRAM End: 0x%x\n", __func__, + (unsigned int)(fb_base + fb_size), + *size); + } else if (fb_base < *start) { + xf86DrvMsg(scrnIndex, X_WARNING, + "%s: FW FB scratch area extends below " + "the base of the free VRAM: 0x%x Base: 0x%x\n", + __func__, (unsigned int)(fb_base), *start); + } else { + *size -= fb_size; + handle->fbBase = fb_base; + return TRUE; + } + } + + if (!handle->fbBase) { + xf86DrvMsg(scrnIndex, X_INFO, + "Cannot get VRAM scratch space. " + "Allocating in main memory instead\n"); + handle->scratchBase = xcalloc(fb_size,1); + return TRUE; + } + return FALSE; +} + +# ifdef ATOM_BIOS_PARSER +static Bool +rhdASICInit(atomBIOSHandlePtr handle) +{ + ASIC_INIT_PS_ALLOCATION asicInit; + AtomBIOSArg data; + + RHDAtomBIOSFunc(handle->scrnIndex, handle, + GET_DEFAULT_ENGINE_CLOCK, + &data); + asicInit.sASICInitClocks.ulDefaultEngineClock = data.val; /* in 10 Khz */ + RHDAtomBIOSFunc(handle->scrnIndex, handle, + GET_DEFAULT_MEMORY_CLOCK, + &data); + asicInit.sASICInitClocks.ulDefaultMemoryClock = data.val; /* in 10 Khz */ + data.exec.dataSpace = NULL; + data.exec.index = 0x0; + data.exec.pspace = &asicInit; + xf86DrvMsg(handle->scrnIndex, X_INFO, "Calling ASIC Init\n"); + if (RHDAtomBIOSFunc(handle->scrnIndex, handle, + ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { + xf86DrvMsg(handle->scrnIndex, X_INFO, "ASIC_INIT Successful\n"); + return TRUE; + } + xf86DrvMsg(handle->scrnIndex, X_INFO, "ASIC_INIT Failed\n"); + return FALSE; +} +# endif + +static atomBIOSHandlePtr +rhdInitAtomBIOS(int scrnIndex) +{ + RADEONInfoPtr info = RADEONPTR(xf86Screens[scrnIndex]); + unsigned char *ptr = info->VBIOS; + atomDataTablesPtr atomDataPtr; + atomBIOSHandlePtr handle = NULL; + unsigned int dummy; + int cmd_offset; + + if (!(atomDataPtr = xcalloc(sizeof(atomDataTables),1))) { + xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory for " + "ATOM BIOS data tabes\n"); + goto error; + } + if (!rhdGetAtombiosDataTable(scrnIndex, ptr, &cmd_offset, atomDataPtr)) + goto error1; + if (!(handle = xcalloc(sizeof(atomBIOSHandle),1))) { + xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory\n"); + goto error1; + } + handle->cmd_offset = cmd_offset; + handle->BIOSBase = ptr; + handle->atomDataPtr = atomDataPtr; + handle->scrnIndex = scrnIndex; +#if XSERVER_LIBPCIACCESS + handle->device = info->PciInfo; +#else + handle->PciTag = info->PciTag; +#endif + +#if ATOM_BIOS_PARSER + /* Try to find out if BIOS has been posted (either by system or int10 */ + if (1 || !rhdBIOSGetFbBaseAndSize(scrnIndex, handle, &dummy, &dummy)) { + /* run AsicInit */ + if (!rhdASICInit(handle)) + xf86DrvMsg(scrnIndex, X_WARNING, + "%s: AsicInit failed. Won't be able to obtain in VRAM " + "FB scratch space\n",__func__); + } +#endif + return handle; + + error1: + xfree(atomDataPtr); + error: + xfree(ptr); + return NULL; +} + +void +rhdTearDownAtomBIOS(int scrnIndex, atomBIOSHandlePtr handle) +{ + // RHDFUNCI(scrnIndex); + + xfree(handle->BIOSBase); + xfree(handle->atomDataPtr); + xfree(handle); +} +AtomBiosResult +rhdAtomBIOSVramInfoQuery(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func, + CARD32 *val) +{ + atomDataTablesPtr atomDataPtr; + + // RHDFUNCI(scrnIndex); + + atomDataPtr = handle->atomDataPtr; + + switch (func) { + case GET_FW_FB_START: + *val = atomDataPtr->VRAM_UsageByFirmware + ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware; + break; + case GET_FW_FB_SIZE: + *val = atomDataPtr->VRAM_UsageByFirmware + ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb; + break; + default: + return ATOM_NOT_IMPLEMENTED; + } + return ATOM_SUCCESS; +} + +AtomBiosResult +rhdAtomBIOSTmdsInfoQuery(int scrnIndex, atomBIOSHandlePtr handle, + AtomBiosFunc func, int index, CARD32 *val) +{ + atomDataTablesPtr atomDataPtr; + + atomDataPtr = handle->atomDataPtr; + if (!rhdGetAtomBiosTableRevisionAndSize( + (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->FirmwareInfo.base), + NULL,NULL,NULL)) { + return ATOM_FAILED; + } + + // RHDFUNCI(scrnIndex); + + switch (func) { + case ATOM_TMDS_FREQUENCY: + *val = atomDataPtr->TMDS_Info->asMiscInfo[index].usFrequency; + break; + case ATOM_TMDS_PLL_CHARGE_PUMP: + *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_ChargePump; + break; + case ATOM_TMDS_PLL_DUTY_CYCLE: + *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_DutyCycle; + break; + case ATOM_TMDS_PLL_VCO_GAIN: + *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_VCO_Gain; + break; + case ATOM_TMDS_PLL_VOLTAGE_SWING: + *val = atomDataPtr->TMDS_Info->asMiscInfo[index].ucPLL_VoltageSwing; + break; + default: + return ATOM_NOT_IMPLEMENTED; + } + return ATOM_SUCCESS; +} + +AtomBiosResult +rhdAtomBIOSFirmwareInfoQuery(int scrnIndex, atomBIOSHandlePtr handle, + AtomBiosFunc func, CARD32 *val) +{ + atomDataTablesPtr atomDataPtr; + CARD8 crev, frev; + + // RHDFUNCI(scrnIndex); + + atomDataPtr = handle->atomDataPtr; + if (!rhdGetAtomBiosTableRevisionAndSize( + (ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->FirmwareInfo.base), + &crev,&frev,NULL)) { + return ATOM_FAILED; + } + switch (crev) { + case 1: + switch (func) { + case GET_DEFAULT_ENGINE_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo->ulDefaultEngineClock; + break; + case GET_DEFAULT_MEMORY_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo->ulDefaultMemoryClock; + break; + case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo->ulMaxPixelClockPLL_Output; + break; + case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo->usMinPixelClockPLL_Output; + case GET_MAX_PIXEL_CLOCK_PLL_INPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo->usMaxPixelClockPLL_Input; + break; + case GET_MIN_PIXEL_CLOCK_PLL_INPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo->usMinPixelClockPLL_Input; + break; + case GET_MAX_PIXEL_CLK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo->usMaxPixelClock; + break; + case GET_REF_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo->usReferenceClock; + break; + default: + return ATOM_NOT_IMPLEMENTED; + } + case 2: + switch (func) { + case GET_DEFAULT_ENGINE_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_2->ulDefaultEngineClock; + break; + case GET_DEFAULT_MEMORY_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_2->ulDefaultMemoryClock; + break; + case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output; + break; + case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_2->usMinPixelClockPLL_Output; + break; + case GET_MAX_PIXEL_CLOCK_PLL_INPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input; + break; + case GET_MIN_PIXEL_CLOCK_PLL_INPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_2->usMinPixelClockPLL_Input; + break; + case GET_MAX_PIXEL_CLK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_2->usMaxPixelClock; + break; + case GET_REF_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_2->usReferenceClock; + break; + default: + return ATOM_NOT_IMPLEMENTED; + } + break; + case 3: + switch (func) { + case GET_DEFAULT_ENGINE_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_3->ulDefaultEngineClock; + break; + case GET_DEFAULT_MEMORY_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_3->ulDefaultMemoryClock; + break; + case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_3->ulMaxPixelClockPLL_Output; + break; + case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_3->usMinPixelClockPLL_Output; + break; + case GET_MAX_PIXEL_CLOCK_PLL_INPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_3->usMaxPixelClockPLL_Input; + break; + case GET_MIN_PIXEL_CLOCK_PLL_INPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_3->usMinPixelClockPLL_Input; + break; + case GET_MAX_PIXEL_CLK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_3->usMaxPixelClock; + break; + case GET_REF_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_3->usReferenceClock; + break; + default: + return ATOM_NOT_IMPLEMENTED; + } + break; + case 4: + switch (func) { + case GET_DEFAULT_ENGINE_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_4->ulDefaultEngineClock; + break; + case GET_DEFAULT_MEMORY_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_4->ulDefaultMemoryClock; + break; + case GET_MAX_PIXEL_CLOCK_PLL_INPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_4->usMaxPixelClockPLL_Input; + break; + case GET_MIN_PIXEL_CLOCK_PLL_INPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_4->usMinPixelClockPLL_Input; + break; + case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_4->ulMaxPixelClockPLL_Output; + break; + case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_4->usMinPixelClockPLL_Output; + break; + case GET_MAX_PIXEL_CLK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_4->usMaxPixelClock; + break; + case GET_REF_CLOCK: + *val = atomDataPtr->FirmwareInfo + .FirmwareInfo_V_1_4->usReferenceClock; + break; + default: + return ATOM_NOT_IMPLEMENTED; + } + break; + default: + return ATOM_NOT_IMPLEMENTED; + } + return ATOM_SUCCESS; +} + +# ifdef ATOM_BIOS_PARSER +static Bool +rhdAtomExec (atomBIOSHandlePtr handle, int index, void *pspace, pointer *dataSpace) +{ + RADEONInfoPtr info = RADEONPTR (xf86Screens[handle->scrnIndex]); + Bool ret = FALSE; + char *msg; + + // RHDFUNCI(handle->scrnIndex); + if (dataSpace) { + if (!handle->fbBase && !handle->scratchBase) + return FALSE; + if (handle->fbBase) { + if (!info->FB) { + xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: " + "Cannot exec AtomBIOS: framebuffer not mapped\n", + __func__); + return FALSE; + } + *dataSpace = (CARD8*)info->FB + handle->fbBase; + } else + *dataSpace = (CARD8*)handle->scratchBase; + } + ret = ParseTableWrapper(pspace, index, handle, + handle->BIOSBase, + &msg); + if (!ret) + xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s\n",msg); + else + xf86DrvMsgVerb(handle->scrnIndex, X_INFO, 5, "%s\n",msg); + + return (ret) ? TRUE : FALSE; +} +# endif + +AtomBiosResult +RHDAtomBIOSFunc(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func, + AtomBIOSArgPtr data) +{ + AtomBiosResult ret = ATOM_NOT_IMPLEMENTED; + CARD32 val; + +# define do_return(x) { \ + if (func < sizeof(AtomBIOSFuncStr)) \ + xf86DrvMsgVerb(scrnIndex, (x == ATOM_SUCCESS) ? 7 : 1, \ + (x == ATOM_SUCCESS) ? X_INFO : X_WARNING, \ + "Call to %s %s\n", AtomBIOSFuncStr[func], \ + (x == ATOM_SUCCESS) ? "succeeded" : "FAILED"); \ + return (x); \ + } + assert (sizeof(AtomBIOSQueryStr) == (FUNC_END - ATOM_QUERY_FUNCS + 1)); + + if (func == ATOMBIOS_INIT) { + if (!(data->atomp = rhdInitAtomBIOS(scrnIndex))) + do_return(ATOM_FAILED); + do_return(ATOM_SUCCESS); + } + if (!handle) + do_return(ATOM_FAILED); + if (func == ATOMBIOS_ALLOCATE_FB_SCRATCH) { + if (rhdAtomBIOSAllocateFbScratch( scrnIndex, handle, &data->fb.start, &data->fb.size)) { + do_return(ATOM_SUCCESS); + } else { + do_return(ATOM_FAILED); + } + } + if (func <= ATOMBIOS_TEARDOWN) { + rhdTearDownAtomBIOS(scrnIndex, handle); + do_return(ATOM_SUCCESS); + } +# ifdef ATOM_BIOS_PARSER + if (func == ATOMBIOS_EXEC) { + if (!rhdAtomExec(handle, data->exec.index, + data->exec.pspace, data->exec.dataSpace)) { + do_return(ATOM_FAILED); + } else { + do_return(ATOM_SUCCESS); + } + } else +# endif + if (func >= ATOM_QUERY_FUNCS && func < ATOM_VRAM_QUERIES) { + ret = rhdAtomBIOSFirmwareInfoQuery(scrnIndex, handle, func, &val); + data->val = val; + } else if (func >= ATOM_VRAM_QUERIES && func < FUNC_END) { + ret = rhdAtomBIOSVramInfoQuery(scrnIndex, handle, func, &val); + data->val = val; + } else { + xf86DrvMsg(scrnIndex,X_INFO,"%s: Received unknown query\n",__func__); + return ATOM_NOT_IMPLEMENTED; + } + if (ret == ATOM_SUCCESS) + xf86DrvMsg(scrnIndex,X_INFO,"%s: %i 0x%08x\n", + AtomBIOSQueryStr[func - ATOM_QUERY_FUNCS], (unsigned int)val, (unsigned int)val); + else + xf86DrvMsg(scrnIndex,X_INFO,"Query for %s: %s\n", + AtomBIOSQueryStr[func - ATOM_QUERY_FUNCS], + ret == ATOM_FAILED ? "failed" : "not implemented"); + return ret; + +} + +# ifdef ATOM_BIOS_PARSER +VOID* +CailAllocateMemory(VOID *CAIL,UINT16 size) +{ + CAILFUNC(CAIL); + + return malloc(size); +} + +VOID +CailReleaseMemory(VOID *CAIL, VOID *addr) +{ + CAILFUNC(CAIL); + + free(addr); +} + +VOID +CailDelayMicroSeconds(VOID *CAIL, UINT32 delay) +{ + CAILFUNC(CAIL); + + usleep(delay); + + // DEBUGP(xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_INFO,"Delay %i usec\n",delay)); +} + +UINT32 +CailReadATIRegister(VOID* CAIL, UINT32 index) +{ + UINT32 ret; + ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + CAILFUNC(CAIL); + + ret = INREG(index << 2); + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index << 2,ret)); + return ret; +} + +VOID +CailWriteATIRegister(VOID *CAIL, UINT32 index, UINT32 data) +{ + CAILFUNC(CAIL); + ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + OUTREG(index << 2,data); + DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index << 2,data)); +} + +UINT32 +CailReadFBData(VOID* CAIL, UINT32 index) +{ + UINT32 ret; + ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + CAILFUNC(CAIL); + + if (((atomBIOSHandlePtr)CAIL)->fbBase) { + CARD8 *FBBase = (CARD8*)info->FB; + ret = *((CARD32*)(FBBase + (((atomBIOSHandlePtr)CAIL)->fbBase) + index)); + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index,ret)); + } else if (((atomBIOSHandlePtr)CAIL)->scratchBase) { + ret = *(CARD32*)((CARD8*)(((atomBIOSHandlePtr)CAIL)->scratchBase) + index); + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index,ret)); + } else { + xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR, + "%s: no fbbase set\n",__func__); + return 0; + } + return ret; +} + +VOID +CailWriteFBData(VOID *CAIL, UINT32 index, UINT32 data) +{ + CAILFUNC(CAIL); + + DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index,data)); + if (((atomBIOSHandlePtr)CAIL)->fbBase) { + CARD8 *FBBase = (CARD8*) + RADEONPTR(xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex])->FB; + *((CARD32*)(FBBase + (((atomBIOSHandlePtr)CAIL)->fbBase) + index)) = data; + } else if (((atomBIOSHandlePtr)CAIL)->scratchBase) { + *(CARD32*)((CARD8*)(((atomBIOSHandlePtr)CAIL)->scratchBase) + index) = data; + } else + xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR, + "%s: no fbbase set\n",__func__); +} + +ULONG +CailReadMC(VOID *CAIL, ULONG Address) +{ + ULONG ret; + ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex]; + CAILFUNC(CAIL); + + ret = AVIVOINMC(pScrn, Address); + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret)); + return ret; +} + +VOID +CailWriteMC(VOID *CAIL, ULONG Address, ULONG data) +{ + CAILFUNC(CAIL); + ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex]; + DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data)); + AVIVOOUTMC(pScrn, Address, data); +} + +VOID +CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 index,UINT16 size) +{ +#if !XSERVER_LIBPCIACCESS + PCITAG tag = ((atomBIOSHandlePtr)CAIL)->PciTag; + + CAILFUNC(CAIL); + + switch (size) { + case 8: + *(CARD8*)ret = pciReadByte(tag,index << 2); + break; + case 16: + *(CARD16*)ret = pciReadWord(tag,index << 2); + break; + case 32: + *(CARD32*)ret = pciReadLong(tag,index << 2); + break; + default: + xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex, + X_ERROR,"%s: Unsupported size: %i\n", + __func__,(int)size); + return; + break; + } +#else + struct pci_device *device = ((atomBIOSHandlePtr)CAIL)->device; + + CAILFUNC(CAIL); + + switch (size) { + case 8: + pci_device_cfg_read_u8(device, (CARD8*)ret, index << 2); + break; + case 16: + pci_device_cfg_read_u16(device, (CARD16*)ret, index << 2); + break; + case 32: + pci_device_cfg_read_u32(device, (uint32_t*)ret, index << 2); + break; + default: + xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex, + X_ERROR,"%s: Unsupported size: %i\n", + __func__,(int)size); + return; + break; + } + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,index,*(unsigned int*)ret)); +#endif +} + +VOID +CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 index,UINT16 size) +{ +#if !XSERVER_LIBPCIACCESS + PCITAG tag = ((atomBIOSHandlePtr)CAIL)->PciTag; + + CAILFUNC(CAIL); + DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index,(*(unsigned int*)src))); + switch (size) { + case 8: + pciWriteByte(tag,index << 2,*(CARD8*)src); + break; + case 16: + pciWriteWord(tag,index << 2,*(CARD16*)src); + break; + case 32: + pciWriteLong(tag,index << 2,*(CARD32*)src); + break; + default: + xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR, + "%s: Unsupported size: %i\n",__func__,(int)size); + break; + } +#else + struct pci_device *device = ((atomBIOSHandlePtr)CAIL)->device; + + CAILFUNC(CAIL); + DEBUGP(ErrorF("%s(%x,%x)\n",__func__,index,(*(unsigned int*)src))); + switch (size) { + case 8: + pci_device_cfg_write_u8(device,index << 2,*(CARD8*)src); + break; + case 16: + pci_device_cfg_write_u16(device,index << 2,*(uint16_t *)src); + break; + case 32: + pci_device_cfg_write_u32(device,index << 2,*(uint32_t *)src); + break; + default: + xf86DrvMsg(((atomBIOSHandlePtr)CAIL)->scrnIndex,X_ERROR, + "%s: Unsupported size: %i\n",__func__,(int)size); + break; + } +#endif +} + +ULONG +CailReadPLL(VOID *CAIL, ULONG Address) +{ + ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + ULONG ret; + + CAILFUNC(CAIL); + + ret = RADEONINPLL(pScrn, Address); + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret)); + return ret; +} + +VOID +CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data) +{ + ScrnInfoPtr pScrn = xf86Screens[((atomBIOSHandlePtr)CAIL)->scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + CAILFUNC(CAIL); + + DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,Data)); + RADEONOUTPLL(pScrn, Address, Data); +} + +void +rhdTestAtomBIOS(atomBIOSHandlePtr atomBIOS) +{ + READ_EDID_FROM_HW_I2C_DATA_PARAMETERS i2cData; + AtomBIOSArg data; + int i; + unsigned char *space; + + i2cData.usPrescale = 0x7fff; + i2cData.usVRAMAddress = 0; + i2cData.usStatus = 128; + i2cData.ucSlaveAddr = 0xA0; + + data.exec.dataSpace = (void*)&space; + data.exec.index = GetIndexIntoMasterTable(COMMAND, ReadEDIDFromHWAssistedI2C); + data.exec.pspace = &i2cData; + + for (i = 0; i < 4; i++) { + i2cData.ucLineNumber = i; + if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { + int j; + CARD8 chksum = 0; + xf86DrvMsg(atomBIOS->scrnIndex, X_INFO,"%s: I2C channel %i STATUS: %x\n", + __func__,i,i2cData.usStatus); + /* read good ? */ + if ((i2cData.usStatus >> 8) == HW_ASSISTED_I2C_STATUS_SUCCESS) { + /* checksum good? */ + ErrorF("i2c data ustatus good %04X\n", i2cData.usStatus); + if (!(i2cData.usStatus & 0xff)) { +#if 0 + RhdDebugDump(atomBIOS->scrnIndex, space, 128); +#endif + for (j = 0; j < 128; j++) + chksum += space[i]; + xf86DrvMsg(atomBIOS->scrnIndex, X_INFO, "DDC Checksum: %i\n",chksum); + } + } + } + } +} +# endif + +#else /* ATOM_BIOS */ + +AtomBiosResult +RHDAtomBIOSFunc(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func, + AtomBIOSArgPtr data) +{ + assert (sizeof(AtomBIOSQueryStr) == (FUNC_END - ATOM_QUERY_FUNCS + 1)); + + if (func < ATOM_QUERY_FUNCS) { + if (func >= 0 && func < sizeof(AtomBIOSFuncStr)) + xf86DrvMsgVerb(scrnIndex, 5, X_WARNING, + "AtomBIOS support not available, cannot execute %s\n", + AtomBIOSFuncStr[func]); + else + xf86DrvMsg(scrnIndex, X_ERROR,"Invalid AtomBIOS func %x\n",func); + } else { + + if (func < FUNC_END) + xf86DrvMsgVerb(scrnIndex, 5, X_WARNING, + "AtomBIOS not available, cannot get %s\n", + AtomBIOSQueryStr[func - ATOM_QUERY_FUNCS]); + else + xf86DrvMsg(scrnIndex, X_ERROR, "Invalid AtomBIOS query %x\n",func); + } + return ATOM_NOT_IMPLEMENTED; +} + +#endif /* ATOM_BIOS */ + + +AtomBiosResult +RADEONAtomBIOSSetCrtcSource(atomBIOSHandlePtr atomBIOS, int crtc, int output_mask) +{ + SELECT_CRTC_SOURCE_PARAMETERS crtc_data; + AtomBIOSArg data; + unsigned char *space; + + crtc_data.ucCRTC = crtc; + crtc_data.ucDevice = ATOM_DEVICE_CRT1_SUPPORT; + + data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); + data.exec.dataSpace = (void *)&space; + data.exec.pspace = &crtc_data; + + if (RHDAtomBIOSFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { + ErrorF("Set CRTC source success\n"); + return ATOM_SUCCESS ; + } + + ErrorF("Set CRTC source failed\n"); + return ATOM_NOT_IMPLEMENTED; +} + +void +atombios_get_command_table_version(atomBIOSHandlePtr atomBIOS, int index, int *major, int *minor) +{ + ATOM_MASTER_COMMAND_TABLE *cmd_table = atomBIOS->BIOSBase + atomBIOS->cmd_offset; + ATOM_MASTER_LIST_OF_COMMAND_TABLES *table_start; + ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *table_hdr; + + unsigned short *ptr; + unsigned short offset; + + table_start = &cmd_table->ListOfCommandTables; + + offset = *(((unsigned short *)table_start) + index); + + table_hdr = atomBIOS->BIOSBase + offset; + + *major = table_hdr->CommonHeader.ucTableFormatRevision; + *minor = table_hdr->CommonHeader.ucTableContentRevision; +} diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h new file mode 100644 index 00000000..b9ce53a5 --- /dev/null +++ b/src/radeon_atombios.h @@ -0,0 +1,202 @@ +/* + * Copyright 2007 Egbert Eich <eich@novell.com> + * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Matthias Hopf <mhopf@novell.com> + * Copyright 2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + + +#ifndef RHD_ATOMBIOS_H_ +# define RHD_ATOMBIOS_H_ + +#include "radeon.h" + +typedef enum { + ATOMBIOS_INIT, + ATOMBIOS_TEARDOWN, + ATOMBIOS_EXEC, + ATOMBIOS_ALLOCATE_FB_SCRATCH, + ATOM_QUERY_FUNCS = 0x1000, + GET_DEFAULT_ENGINE_CLOCK = ATOM_QUERY_FUNCS, + GET_DEFAULT_MEMORY_CLOCK, + GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, + GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, + GET_MAX_PIXEL_CLOCK_PLL_INPUT, + GET_MIN_PIXEL_CLOCK_PLL_INPUT, + GET_MAX_PIXEL_CLK, + GET_REF_CLOCK, + ATOM_VRAM_QUERIES, + GET_FW_FB_START = ATOM_VRAM_QUERIES, + GET_FW_FB_SIZE, + ATOM_TMDS_QUERIES, + ATOM_TMDS_FREQUENCY = ATOM_TMDS_QUERIES, + ATOM_TMDS_PLL_CHARGE_PUMP, + ATOM_TMDS_PLL_DUTY_CYCLE, + ATOM_TMDS_PLL_VCO_GAIN, + ATOM_TMDS_PLL_VOLTAGE_SWING, + FUNC_END +} AtomBiosFunc; + +typedef enum { + ATOM_SUCCESS, + ATOM_FAILED, + ATOM_NOT_IMPLEMENTED +} AtomBiosResult; + +typedef struct { + int index; + pointer pspace; + pointer *dataSpace; +} AtomExec, *AtomExecPtr; + +typedef struct { + unsigned int start; + unsigned int size; +} AtomFb, *AtomFbPtr; + +typedef union +{ + CARD32 val; + + pointer ptr; + atomBIOSHandlePtr atomp; + AtomExec exec; + AtomFb fb; +} AtomBIOSArg, *AtomBIOSArgPtr; + + +extern void +atombios_get_command_table_version(atomBIOSHandlePtr atomBIOS, int index, int *major, int *minor); + +extern AtomBiosResult +RHDAtomBIOSFunc(int scrnIndex, atomBIOSHandlePtr handle, AtomBiosFunc func, + AtomBIOSArgPtr data); + +/* only for testing */ +void rhdTestAtomBIOS(atomBIOSHandlePtr atomBIOS); + +#ifdef ATOM_BIOS +//# include "rhd_atomwrapper.h" +# include "xf86int10.h" +# ifdef ATOM_BIOS_PARSER +# define INT8 INT8 +# define INT16 INT16 +# define INT32 INT32 +# include "CD_Common_Types.h" +# else +# ifndef ULONG +typedef unsigned int ULONG; +# define ULONG ULONG +# endif +# ifndef UCHAR +typedef unsigned char UCHAR; +# define UCHAR UCHAR +# endif +# ifndef USHORT +typedef unsigned short USHORT; +# define USHORT USHORT +# endif +# endif + +#include "atombios.h" + + +typedef struct _atomDataTables +{ + unsigned char *UtilityPipeLine; + ATOM_MULTIMEDIA_CAPABILITY_INFO *MultimediaCapabilityInfo; + ATOM_MULTIMEDIA_CONFIG_INFO *MultimediaConfigInfo; + ATOM_STANDARD_VESA_TIMING *StandardVESA_Timing; + union { + void *base; + ATOM_FIRMWARE_INFO *FirmwareInfo; + ATOM_FIRMWARE_INFO_V1_2 *FirmwareInfo_V_1_2; + ATOM_FIRMWARE_INFO_V1_3 *FirmwareInfo_V_1_3; + ATOM_FIRMWARE_INFO_V1_4 *FirmwareInfo_V_1_4; + } FirmwareInfo; + ATOM_DAC_INFO *DAC_Info; + union { + void *base; + ATOM_LVDS_INFO *LVDS_Info; + ATOM_LVDS_INFO_V12 *LVDS_Info_v12; + } LVDS_Info; + ATOM_TMDS_INFO *TMDS_Info; + ATOM_ANALOG_TV_INFO *AnalogTV_Info; + union { + void *base; + ATOM_SUPPORTED_DEVICES_INFO *SupportedDevicesInfo; + ATOM_SUPPORTED_DEVICES_INFO_2 *SupportedDevicesInfo_2; + ATOM_SUPPORTED_DEVICES_INFO_2d1 *SupportedDevicesInfo_2d1; + } SupportedDevicesInfo; + ATOM_GPIO_I2C_INFO *GPIO_I2C_Info; + ATOM_VRAM_USAGE_BY_FIRMWARE *VRAM_UsageByFirmware; + ATOM_GPIO_PIN_LUT *GPIO_Pin_LUT; + ATOM_VESA_TO_INTENAL_MODE_LUT *VESA_ToInternalModeLUT; + union { + void *base; + ATOM_COMPONENT_VIDEO_INFO *ComponentVideoInfo; + ATOM_COMPONENT_VIDEO_INFO_V21 *ComponentVideoInfo_v21; + } ComponentVideoInfo; +/**/unsigned char *PowerPlayInfo; + COMPASSIONATE_DATA *CompassionateData; + ATOM_DISPLAY_DEVICE_PRIORITY_INFO *SaveRestoreInfo; +/**/unsigned char *PPLL_SS_Info; + ATOM_OEM_INFO *OemInfo; + ATOM_XTMDS_INFO *XTMDS_Info; + ATOM_ASIC_MVDD_INFO *MclkSS_Info; + ATOM_OBJECT_HEADER *Object_Header; + INDIRECT_IO_ACCESS *IndirectIOAccess; + ATOM_MC_INIT_PARAM_TABLE *MC_InitParameter; +/**/unsigned char *ASIC_VDDC_Info; + ATOM_ASIC_INTERNAL_SS_INFO *ASIC_InternalSS_Info; +/**/unsigned char *TV_VideoMode; + union { + void *base; + ATOM_VRAM_INFO_V2 *VRAM_Info_v2; + ATOM_VRAM_INFO_V3 *VRAM_Info_v3; + } VRAM_Info; + ATOM_MEMORY_TRAINING_INFO *MemoryTrainingInfo; + union { + void *base; + ATOM_INTEGRATED_SYSTEM_INFO *IntegratedSystemInfo; + ATOM_INTEGRATED_SYSTEM_INFO_V2 *IntegratedSystemInfo_v2; + } IntegratedSystemInfo; + ATOM_ASIC_PROFILING_INFO *ASIC_ProfilingInfo; + ATOM_VOLTAGE_OBJECT_INFO *VoltageObjectInfo; + ATOM_POWER_SOURCE_INFO *PowerSourceInfo; +} atomDataTables, *atomDataTablesPtr; + +typedef struct _atomBIOSHandle { + int scrnIndex; + unsigned char *BIOSBase; + atomDataTablesPtr atomDataPtr; + pointer *scratchBase; + CARD32 fbBase; + int cmd_offset; +#if XSERVER_LIBPCIACCESS + struct pci_device *device; +#else + PCITAG PciTag; +#endif +} atomBIOSHandle; + +#endif +#endif /* RHD_ATOMBIOS_H_ */ diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c new file mode 100644 index 00000000..cdcb5322 --- /dev/null +++ b/src/radeon_atomwrapper.c @@ -0,0 +1,97 @@ +/* + * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Matthias Hopf <mhopf@novell.com> + * Copyright 2007 Egbert Eich <eich@novell.com> + * Copyright 2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "radeon_atomwrapper.h" + +#define INT32 INT32 +#include "CD_Common_Types.h" +#include "CD_Definitions.h" + + +int +ParseTableWrapper(void *pspace, int index, void *handle, void *BIOSBase, + char **msg_return) +{ + DEVICE_DATA deviceData; + int ret = 0; + + /* FILL OUT PARAMETER SPACE */ + deviceData.pParameterSpace = (UINT32*) pspace; + deviceData.CAIL = handle; + deviceData.pBIOS_Image = BIOSBase; + deviceData.format = TABLE_FORMAT_BIOS; + + switch (ParseTable(&deviceData, index)) { /* IndexInMasterTable */ + case CD_SUCCESS: + ret = 1; + *msg_return = "ParseTable said: CD_SUCCESS"; + break; + case CD_CALL_TABLE: + ret = 1; + *msg_return = "ParseTable said: CD_CALL_TABLE"; + break; + case CD_COMPLETED: + ret = 1; + *msg_return = "ParseTable said: CD_COMPLETED"; + break; + case CD_GENERAL_ERROR: + ret = 0; + *msg_return = " ParseTable said: CD_GENERAL_ERROR"; + break; + case CD_INVALID_OPCODE: + ret = 0; + *msg_return = " ParseTable said: CD_INVALID_OPCODE"; + break; + case CD_NOT_IMPLEMENTED: + ret = 0; + *msg_return = " ParseTable said: CD_NOT_IMPLEMENTED"; + break; + case CD_EXEC_TABLE_NOT_FOUND: + ret = 0; + *msg_return = " ParseTable said: CD_EXEC_TABLE_NOT_FOUND"; + break; + case CD_EXEC_PARAMETER_ERROR: + ret = 0; + *msg_return = " ParseTable said: CD_EXEC_PARAMETER_ERROR"; + break; + case CD_EXEC_PARSER_ERROR: + ret = 0; + *msg_return = " ParseTable said: CD_EXEC_PARSER_ERROR"; + break; + case CD_INVALID_DESTINATION_TYPE: + ret = 0; + *msg_return = " ParseTable said: CD_INVALID_DESTINATION_TYPE"; + break; + case CD_UNEXPECTED_BEHAVIOR: + ret = 0; + *msg_return = " ParseTable said: CD_UNEXPECTED_BEHAVIOR"; + break; + case CD_INVALID_SWITCH_OPERAND_SIZE: + ret = 0; + *msg_return = " ParseTable said: CD_INVALID_SWITCH_OPERAND_SIZE\n"; + break; + } + return ret; +} diff --git a/src/radeon_atomwrapper.h b/src/radeon_atomwrapper.h new file mode 100644 index 00000000..1e7cc773 --- /dev/null +++ b/src/radeon_atomwrapper.h @@ -0,0 +1,31 @@ +/* + * Copyright 2007 Luc Verhaegen <lverhaegen@novell.com> + * Copyright 2007 Matthias Hopf <mhopf@novell.com> + * Copyright 2007 Egbert Eich <eich@novell.com> + * Copyright 2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef RHD_ATOMWRAPPER_H_ +# define RHD_ATOMWRAPPER_H_ + +extern int ParseTableWrapper(void *pspace, int index, void *CAIL, + void *BIOSBase, char **msg_return); + +#endif /* RHD_ATOMWRAPPER_H_ */ diff --git a/src/radeon_probe.h b/src/radeon_probe.h index 66ece941..78fc9ffc 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h @@ -168,6 +168,15 @@ typedef struct _RADEONCrtcPrivateRec { int binding; /* Lookup table values to be set when the CRTC is enabled */ CARD8 lut_r[256], lut_g[256], lut_b[256]; + + uint32_t crtc_offset; + int h_total, h_blank, h_sync_wid, h_sync_pol; + int v_total, v_blank, v_sync_wid, v_sync_pol; + int fb_format, fb_length; + int fb_pitch, fb_width, fb_height; + INT16 cursor_x; + INT16 cursor_y; + unsigned long cursor_offset; } RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr; typedef struct { @@ -176,6 +185,7 @@ typedef struct { RADEONTmdsType TMDSType; RADEONConnectorType ConnectorType; Bool valid; + int gpio; } RADEONBIOSConnector; typedef struct _RADEONOutputPrivateRec { @@ -221,6 +231,9 @@ typedef struct _RADEONOutputPrivateRec { int SupportedTVStds; Bool tv_on; int load_detection; + + unsigned long gpio; + char *name; } RADEONOutputPrivateRec, *RADEONOutputPrivatePtr; #define RADEON_MAX_CRTC 2 |