diff options
| author | Alex Deucher <alex@botch2.(none)> | 2007-09-20 23:49:57 -0400 |
|---|---|---|
| committer | Alex Deucher <alex@botch2.(none)> | 2007-09-20 23:49:57 -0400 |
| commit | c72a365386e19f9257db041d44b09ad499cc9f6a (patch) | |
| tree | 85c21c996d0ccd627178952b68d51b8219e9844d | |
| parent | 5e4d98470b6412a686883c554e7eb7badbe78c4d (diff) | |
RADEON: fix up dvo support (still no external chip init)
| -rw-r--r-- | src/radeon_display.c | 7 | ||||
| -rw-r--r-- | src/radeon_output.c | 23 |
2 files changed, 16 insertions, 14 deletions
diff --git a/src/radeon_display.c b/src/radeon_display.c index fa80e104..7f599e69 100644 --- a/src/radeon_display.c +++ b/src/radeon_display.c @@ -289,6 +289,7 @@ void RADEONDisableDisplays(ScrnInfoPtr pScrn) { /* FP 2 */ tmp = INREG(RADEON_FP2_GEN_CNTL); + tmp |= RADEON_FP2_BLANK_EN; tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); OUTREG(RADEON_FP2_GEN_CNTL, tmp); @@ -355,10 +356,12 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); } else if (radeon_output->TMDSType == TMDS_EXT) { tmp = INREG(RADEON_FP2_GEN_CNTL); + tmp &= ~RADEON_FP2_BLANK_EN; tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); OUTREG(RADEON_FP2_GEN_CNTL, tmp); save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); - } + save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; + } } else if (radeon_output->MonType == MT_LCD) { tmp = INREG(RADEON_LVDS_GEN_CNTL); tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON); @@ -406,9 +409,11 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); } else if (radeon_output->TMDSType == TMDS_EXT) { tmp = INREG(RADEON_FP2_GEN_CNTL); + tmp |= RADEON_FP2_BLANK_EN; tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); OUTREG(RADEON_FP2_GEN_CNTL, tmp); save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); + save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN; } } else if (radeon_output->MonType == MT_LCD) { unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); diff --git a/src/radeon_output.c b/src/radeon_output.c index f9a21bbf..8b7ae087 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -766,7 +766,7 @@ static void RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, DisplayModePtr mode, BOOL IsPrimary) { ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); if (pScrn->rgbBits == 8) @@ -776,26 +776,23 @@ static void RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl & ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ - save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); + save->fp2_gen_cntl &= ~(RADEON_FP2_ON | + RADEON_FP2_DVO_EN | + RADEON_FP2_DVO_RATE_SEL_SDR); if (IsPrimary) { if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { - save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | - RADEON_FP2_DVO_EN | - RADEON_FP2_DVO_RATE_SEL_SDR); - if (mode->Flags & RADEON_USE_RMX) - save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; + save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; + if (mode->Flags & RADEON_USE_RMX) + save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; } else { - save->fp2_gen_cntl &= ~(RADEON_FP2_SRC_SEL_CRTC2 | - RADEON_FP2_DVO_RATE_SEL_SDR); - } + save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; + } } else { if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { - save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | - RADEON_FP2_DVO_RATE_SEL_SDR); + save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; } else { - save->fp2_gen_cntl &= ~(RADEON_FP2_DVO_RATE_SEL_SDR); save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; } } |