radeon: cleanup some pieces of the dpms/blank register programming

1 files changed, 31 insertions, 52 deletions

diff --git a/src/radeon_display.c b/src/radeon_display.c
index 0bf72711..95e669d4 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -2020,33 +2020,26 @@ RADEONOutputsBlank(ScrnInfoPtr pScrn, RADEONConnector *pPort, Bool Blank)
 {
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
     unsigned char *RADEONMMIO = info->MMIO;
+    CARD32 val;
 
     switch(pPort->MonType) {
     case MT_LCD:
-	if (Blank)
-	    OUTREGP(RADEON_LVDS_GEN_CNTL, RADEON_LVDS_DISPLAY_DIS, ~RADEON_LVDS_DISPLAY_DIS);
-	else
-	    OUTREGP(RADEON_LVDS_GEN_CNTL, 0, ~RADEON_LVDS_DISPLAY_DIS);
+	val = (Blank == TRUE) ? RADEON_LVDS_DISPLAY_DIS : 0;
+	OUTREGP(RADEON_LVDS_GEN_CNTL, val, ~RADEON_LVDS_DISPLAY_DIS);
         break;
     case MT_CRT:
 	if ((info->ChipFamily == CHIP_FAMILY_R200) && (pPort->DACType == DAC_TVDAC)) {
-	    if (Blank)
-		OUTREGP(RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN);
-	    else
-		OUTREGP(RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);
+	    val = (Blank == TRUE) ? RADEON_FP2_BLANK_EN : 0;
+	    OUTREGP(RADEON_FP2_GEN_CNTL, val, ~RADEON_FP2_BLANK_EN);
 	}
         break;
     case MT_DFP:
 	if (pPort->TMDSType == TMDS_EXT) {
-	    if (Blank)
-		OUTREGP(RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN);
-	    else
-		OUTREGP(RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);
+	    val = Blank ? RADEON_FP2_BLANK_EN : 0;
+	    OUTREGP(RADEON_FP2_GEN_CNTL, val, ~RADEON_FP2_BLANK_EN);
 	} else {
-	    if (Blank)
-		OUTREGP(RADEON_FP_GEN_CNTL, RADEON_FP_BLANK_EN, ~RADEON_FP_BLANK_EN);
-	    else
-		OUTREGP(RADEON_FP_GEN_CNTL, 0, ~RADEON_FP_BLANK_EN);
+	    val = Blank ? RADEON_FP_BLANK_EN : 0;
+	    OUTREGP(RADEON_FP_GEN_CNTL, val, ~RADEON_FP_BLANK_EN);
 	}
         break;
     case MT_NONE:
@@ -2059,28 +2052,19 @@ static void
 RADEONCRTC1Blank(RADEONInfoPtr info, Bool Blank)
 {
     unsigned char *RADEONMMIO = info->MMIO;
-    
-    if (Blank)
-	OUTREGP(RADEON_CRTC_EXT_CNTL,
-		RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS,
-		~(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS));
-    else
-	OUTREGP(RADEON_CRTC_EXT_CNTL, 0,
-		~(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS));
+    CARD32 val = (Blank == TRUE) ? (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS) : 0;
+
+    OUTREGP(RADEON_CRTC_EXT_CNTL, val,
+	    ~(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS));
 }
 
 static void
 RADEONCRTC2Blank(RADEONInfoPtr info, Bool Blank)
 {
     unsigned char *RADEONMMIO = info->MMIO;
-    
-    if (Blank)
-	OUTREGP(RADEON_CRTC2_GEN_CNTL,
-		RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS,
-		~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS));
-    else
-	OUTREGP(RADEON_CRTC2_GEN_CNTL, 0,
-		~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS));
+    CARD32 val = (Blank == TRUE) ? (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS) : 0;
+    OUTREGP(RADEON_CRTC2_GEN_CNTL, val,
+	    ~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS));
 }
 
 /* Blank screen */
@@ -2178,63 +2162,58 @@ void
 RADEONCRTC1DPMS(RADEONInfoPtr info, int Mode)
 {
     unsigned char *RADEONMMIO = info->MMIO;
-
+    CARD32 val;
     switch (Mode) {
 	case DPMSModeOn:
 	    /* Screen: On; HSync: On, VSync: On */
-	    OUTREGP(RADEON_CRTC_EXT_CNTL, 0,
-		    ~(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS));
+	    val = 0;
 	    break;
 	case DPMSModeStandby:
 	    /* Screen: Off; HSync: Off, VSync: On */
-	    OUTREGP(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS),
-		    ~(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS));
+	    val = (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS);
 	    break;
 	case DPMSModeSuspend:
 	    /* Screen: Off; HSync: On, VSync: Off */
-	    OUTREGP(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS),
-		    ~(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS));
+	    val = (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS);
 	    break;
 	case DPMSModeOff:
 	default:
 	    /* Screen: Off; HSync: Off, VSync: Off */
-	    OUTREGP(RADEON_CRTC_EXT_CNTL,
-		    (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS),
-		    ~(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS));
+	    val = (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS);
 	    break;
     }
+    OUTREGP(RADEON_CRTC_EXT_CNTL, val,
+	    ~(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS));
+
 }
 
 void
 RADEONCRTC2DPMS(RADEONInfoPtr info, int Mode)
 {
     unsigned char *RADEONMMIO = info->MMIO;
-    
+    CARD32 val;
     switch (Mode) {
 	case DPMSModeOn:
 	    /* Screen: On; HSync: On, VSync: On */
-	    OUTREGP(RADEON_CRTC2_GEN_CNTL, 0,
-		    ~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS));
+	    val = 0;
 	    break;
 	case DPMSModeStandby:
 	    /* Screen: Off; HSync: Off, VSync: On */
-	    OUTREGP(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS),
-		    ~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS));
+	    val = (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS);
 	    break;
 	case DPMSModeSuspend:
 	    /* Screen: Off; HSync: On, VSync: Off */
-	    OUTREGP(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS),
-		    ~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS));
+	    val = (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS);
 	    break;
 	case DPMSModeOff:
 	default:
 	    /* Screen: Off; HSync: Off, VSync: Off */
-	    OUTREGP(RADEON_CRTC2_GEN_CNTL,
-		    (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS),
-		    ~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS));
+	    val = (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS);
 	    break;
 	    
     }
+    OUTREGP(RADEON_CRTC2_GEN_CNTL, val,
+	    ~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS));    
 }