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authorMichel Dänzer <michel.daenzer@amd.com>2011-10-27 19:12:22 +0200
committerMichel Dänzer <michel@daenzer.net>2011-10-27 19:30:25 +0200
commit23788c4a5e3b6affb9b183e1393edd0e5ca4550e (patch)
treec46828df48757ed77fc96eb357cfc2f0d5a1e3d7
parent6e0e1a821accc6ca95f4134e49b66a6b168c1934 (diff)
EXA < R6xx: Make sure 2D state is re-emitted after running out of CS space.
Otherwise it's basically luck what the 2D state ends up being at the beginning of the next CS. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
-rw-r--r--src/radeon_exa_funcs.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 52adcea6..058a547b 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -132,14 +132,13 @@ static void FUNC_NAME(Emit2DState)(ScrnInfoPtr pScrn, int op)
}
static void
-FUNC_NAME(RADEONDone2D)(PixmapPtr pPix)
+FUNC_NAME(RADEONFlush2D)(PixmapPtr pPix)
{
RINFO_FROM_SCREEN(pPix->drawable.pScreen);
ACCEL_PREAMBLE();
TRACE;
- info->state_2d.op = 0;
BEGIN_ACCEL(2);
OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
OUT_ACCEL_REG(RADEON_WAIT_UNTIL,
@@ -147,6 +146,15 @@ FUNC_NAME(RADEONDone2D)(PixmapPtr pPix)
FINISH_ACCEL();
}
+static void
+FUNC_NAME(RADEONDone2D)(PixmapPtr pPix)
+{
+ RINFO_FROM_SCREEN(pPix->drawable.pScreen);
+ info->state_2d.op = 0;
+
+ FUNC_NAME(RADEONFlush2D)(pPix);
+}
+
static Bool
FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
{
@@ -220,7 +228,7 @@ FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2)
#if defined(ACCEL_CP) && defined(XF86DRM_MODE)
if (info->cs && CS_FULL(info->cs)) {
- FUNC_NAME(RADEONDone2D)(info->accel_state->dst_pix);
+ FUNC_NAME(RADEONFlush2D)(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
}
#endif
@@ -332,7 +340,7 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst,
#if defined(ACCEL_CP) && defined(XF86DRM_MODE)
if (info->cs && CS_FULL(info->cs)) {
- FUNC_NAME(RADEONDone2D)(info->accel_state->dst_pix);
+ FUNC_NAME(RADEONFlush2D)(info->accel_state->dst_pix);
radeon_cs_flush_indirect(pScrn);
}
#endif