radeon: r6xx-eg use linear general when using scratch bo

In path where we need to use scratch bo as temporary area,
consider it as linear buffer. Not linear aligned. Fix some
case such as in bugs:

https://bugs.freedesktop.org/show_bug.cgi?id=45827

Signed-off-by: Jerome Glisse <jglisse@redhat.com>

4 files changed, 11 insertions, 11 deletions

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 7fa89de2..3a23474b 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -87,7 +87,7 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
 			surface->nsamples = 1;
 			surface->flags = RADEON_SURF_SCANOUT;
 			surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-			surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
+			surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
 			if (tiling & RADEON_TILING_MICRO) {
 				surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
 				surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
@@ -1293,7 +1293,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 		surface.nsamples = 1;
 		surface.flags = RADEON_SURF_SCANOUT;
 		surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-		surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
+		surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
 		if (tiling_flags & RADEON_TILING_MICRO) {
 			surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
 			surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 97810693..1077a2dd 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -161,7 +161,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
 	cb_conf.pmask |= 8; /* A */
     cb_conf.rop = accel_state->rop;
     if (accel_state->dst_obj.tiling_flags == 0) {
-	cb_conf.array_mode = 1;
+	cb_conf.array_mode = 0;
 	cb_conf.non_disp_tiling = 1;
     }
     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
@@ -340,7 +340,7 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
     tex_res.last_level          = 0;
     tex_res.perf_modulation     = 0;
     if (accel_state->src_obj[0].tiling_flags == 0)
-	tex_res.array_mode          = 1;
+	tex_res.array_mode          = 0;
     evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
 
     tex_samp.id                 = 0;
@@ -383,7 +383,7 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
 	cb_conf.pmask |= 8; /* A */
     cb_conf.rop = accel_state->rop;
     if (accel_state->dst_obj.tiling_flags == 0) {
-	cb_conf.array_mode = 1;
+	cb_conf.array_mode = 0;
 	cb_conf.non_disp_tiling = 1;
     }
     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
@@ -999,7 +999,7 @@ static Bool EVERGREENTextureSetup(PicturePtr pPict, PixmapPtr pPix,
     tex_res.last_level          = 0;
     tex_res.perf_modulation     = 0;
     if (accel_state->src_obj[unit].tiling_flags == 0)
-	tex_res.array_mode          = 1;
+	tex_res.array_mode          = 0;
     evergreen_set_tex_resource  (pScrn, &tex_res, accel_state->src_obj[unit].domain);
 
     tex_samp.id                 = unit;
@@ -1313,7 +1313,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
     cb_conf.rop = 3;
     cb_conf.pmask = 0xf;
     if (accel_state->dst_obj.tiling_flags == 0) {
-	cb_conf.array_mode = 1;
+	cb_conf.array_mode = 0;
 	cb_conf.non_disp_tiling = 1;
     }
 #if X_BYTE_ORDER == X_BIG_ENDIAN
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 8a538964..e1eb62f1 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -278,7 +278,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
 	cb_conf.pmask |= 8; /* A */
     cb_conf.rop = accel_state->rop;
     if (accel_state->dst_obj.tiling_flags == 0)
-	cb_conf.array_mode = 1;
+	cb_conf.array_mode = 0;
     r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
 
     r600_set_spi(pScrn, accel_state->ib, 0, 0);
@@ -501,7 +501,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
 	cb_conf.pmask |= 8; /* A */
     cb_conf.rop = accel_state->rop;
     if (accel_state->dst_obj.tiling_flags == 0)
-	cb_conf.array_mode = 1;
+	cb_conf.array_mode = 0;
     r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
 
     r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
@@ -1476,7 +1476,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
     cb_conf.pmask = 0xf;
     cb_conf.rop = 3;
     if (accel_state->dst_obj.tiling_flags == 0)
-	cb_conf.array_mode = 1;
+	cb_conf.array_mode = 0;
 #if X_BYTE_ORDER == X_BIG_ENDIAN
     switch (dst_obj.bpp) {
     case 16:
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index b5f13a23..124ce800 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -1262,7 +1262,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
 		surface.nsamples = 1;
 		surface.flags = RADEON_SURF_SCANOUT;
 		surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-		surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
+		surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
 		if (tiling_flags & RADEON_TILING_MICRO) {
 			surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
 			surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);