r500: initial rotate support - not fully working yet.

Just an example of how to setup and run the r500 3D engine for rotation.
this rotates for me but I get some strange clipping on the bottom of my screen

4 files changed, 103 insertions, 31 deletions

diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 629336f0..a626bbd4 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -57,7 +57,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 
     info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
 
-    if (IS_R300_VARIANT) {
+    if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
 	BEGIN_ACCEL(3);
 	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
 	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3);
@@ -91,14 +91,12 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(R300_GA_OFFSET, 0x0);
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(7);
+	BEGIN_ACCEL(5);
 	OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0x0);
 	OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0x0);
 	OUT_ACCEL_REG(R300_SU_CULL_MODE, 0x4);
 	OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff);
 	OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0x0);
-	OUT_ACCEL_REG(R300_RS_COUNT, 0x40002);
-	OUT_ACCEL_REG(R300_RS_IP_0, 0x1610000);
 	FINISH_ACCEL();
 
 	BEGIN_ACCEL(5);
@@ -109,10 +107,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(R300_US_OUT_FMT_0, 0x1B01);
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(2);
-	OUT_ACCEL_REG(R300_RS_INST_COUNT, 0xC0);
-	OUT_ACCEL_REG(R300_RS_INST_0, 0x8);
-	FINISH_ACCEL();
 
 	BEGIN_ACCEL(3);
 	OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0x0);
@@ -140,8 +134,13 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
 	OUT_ACCEL_REG(R300_SC_SCISSOR0, 0x0);
 	OUT_ACCEL_REG(R300_SC_SCISSOR1, 0x3ffffff);
-	OUT_ACCEL_REG(R300_SC_CLIP_0_A, 0x880440);
-	OUT_ACCEL_REG(R300_SC_CLIP_0_B, 0xff0ff0);
+	if (IS_AVIVO_VARIANT) {
+		OUT_ACCEL_REG(R300_SC_CLIP_0_A, 0x0);
+		OUT_ACCEL_REG(R300_SC_CLIP_0_B, 0xff0ff0);
+	} else {
+		OUT_ACCEL_REG(R300_SC_CLIP_0_A, 0x880440);
+		OUT_ACCEL_REG(R300_SC_CLIP_0_B, 0xff0ff0);
+	}
 	OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
 	OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff);
 	FINISH_ACCEL();
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 20b96a5d..ce50dfd5 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -533,11 +533,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
 
 #ifdef RENDER
     if (info->RenderAccel) {
-	if ((info->ChipFamily >= CHIP_FAMILY_RV515) ||
+	if ((info->ChipFamily >= CHIP_FAMILY_RS690) ||
 	    (info->ChipFamily == CHIP_FAMILY_RS400))
 		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
 			       "unsupported on XPRESS, R500 and newer cards.\n");
-	else if (IS_R300_VARIANT) {
+	else if (IS_R300_VARIANT || info->ChipFamily < CHIP_FAMILY_RS690) {
 		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
 			       "enabled for R300 type cards.\n");
 		info->exa->CheckComposite = R300CheckComposite;
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 9b23cdcf..d16a2690 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1009,21 +1009,55 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
     OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, 0x10000);
     FINISH_ACCEL();
 
-    /* setup pixel shader */
-    BEGIN_ACCEL(12);
-    OUT_ACCEL_REG(R300_US_CONFIG, 0x8);
-    OUT_ACCEL_REG(R300_US_PIXSIZE, 0x0);
-    OUT_ACCEL_REG(R300_US_CODE_OFFSET, 0x40040);
-    OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0x0);
-    OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0x0);
-    OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0x0);
-    OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000);
-    OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000);
-    OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000);
-    OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, 0x50a80);
-    OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000);
-    OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889);
-    FINISH_ACCEL();
+    if (IS_R300_VARIANT) {
+      /* setup pixel shader */
+      BEGIN_ACCEL(16);
+      OUT_ACCEL_REG(R300_RS_COUNT, 0x40002);
+      OUT_ACCEL_REG(R300_RS_IP_0, 0x1610000);
+      OUT_ACCEL_REG(R300_RS_INST_COUNT, 0xC0);
+      OUT_ACCEL_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
+      OUT_ACCEL_REG(R300_US_CONFIG, 0x8);
+      OUT_ACCEL_REG(R300_US_PIXSIZE, 0x0);
+      OUT_ACCEL_REG(R300_US_CODE_OFFSET, 0x40040);
+      OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0x0);
+      OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0x0);
+      OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0x0);
+      OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000);
+      OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000);
+      OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000);
+      OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, 0x50a80);
+      OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000);
+      OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889);
+      FINISH_ACCEL();
+    } else {
+      BEGIN_ACCEL(22);
+      OUT_ACCEL_REG(R300_RS_COUNT, 0x40002);
+      OUT_ACCEL_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+		    (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
+
+      OUT_ACCEL_REG(R300_RS_INST_COUNT, 0x0);
+      OUT_ACCEL_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
+      OUT_ACCEL_REG(R300_US_CONFIG, 0x2);
+      OUT_ACCEL_REG(R300_US_PIXSIZE, 0x0);
+      OUT_ACCEL_REG(R500_US_FC_CTRL, 0x0);
+      OUT_ACCEL_REG(R500_US_CODE_ADDR, 0x10000);
+      OUT_ACCEL_REG(R500_US_CODE_RANGE, 0x10000);
+      OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0x0);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0x0);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00007807);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x06400000);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0xe4000400);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00078105);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x10040000);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x10040000);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00db0220);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00c0c000);
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x20490000);
+      FINISH_ACCEL();
+    }
 
     BEGIN_ACCEL(6);
     OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
@@ -1178,7 +1212,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
 
     vtx_count = VTX_COUNT;
 
-    if (IS_R300_VARIANT) {
+    if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
 	BEGIN_ACCEL(1);
 	OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count);
 	FINISH_ACCEL();
@@ -1198,7 +1232,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
 		 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
 		 (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
     } else {
-	if (IS_R300_VARIANT)
+	if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
 	    BEGIN_RING(4 * vtx_count + 6);
 	else
 	    BEGIN_RING(4 * vtx_count + 2);
@@ -1211,7 +1245,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
     }
 
 #else /* ACCEL_CP */
-    if (IS_R300_VARIANT)
+    if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
 	BEGIN_ACCEL(3 + vtx_count * 4);
     else
 	BEGIN_ACCEL(1 + vtx_count * 4);
@@ -1241,7 +1275,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
 	    xFixedToFloat(srcTopRight.x) / info->texW[0],     xFixedToFloat(srcTopRight.y) / info->texH[0],
 	    xFixedToFloat(maskTopRight.x) / info->texW[1],    xFixedToFloat(maskTopRight.y) / info->texH[1]);
 
-    if (IS_R300_VARIANT) {
+    if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
 	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
 	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
     }
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 5469e9d5..f89a9eb9 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3860,9 +3860,14 @@
 #define R300_SU_DEPTH_OFFSET			        0x42c4
 
 #define R300_RS_COUNT				        0x4300
+#	define R300_RS_COUNT_IT_COUNT_SHIFT		0
+#	define R300_RS_COUNT_IC_COUNT_SHIFT		7
+#	define R300_RS_COUNT_HIRES_EN			(1<<18)
+
 #define R300_RS_IP_0				        0x4310
 #define R300_RS_INST_COUNT				0x4304
 #define R300_RS_INST_0				        0x4330
+#define R300_RS_INST_TEX_CN_WRITE 			(1 << 3)
 
 #define R300_TX_INVALTAGS				0x4100
 #define R300_TX_FILTER0_0				0x4400
@@ -4505,4 +4510,38 @@
 #   define R500_W_SRC_US				(0 << 2)
 #   define R500_W_SRC_RAS				(1 << 2)
 
+#define R500_GA_US_VECTOR_INDEX 0x4250
+#define R500_GA_US_VECTOR_DATA 0x4254
+
+#define R500_RS_INST_0					0x4320
+#define R500_RS_INST_TEX_ID_SHIFT			0
+#define R500_RS_INST_TEX_CN_WRITE			(1 << 4)
+#define R500_RS_INST_TEX_ADDR_SHIFT			5
+#define R500_RS_INST_COL_ID_SHIFT			12
+#define R500_RS_INST_COL_CN_NO_WRITE			(0 << 16)
+#define R500_RS_INST_COL_CN_WRITE			(1 << 16)
+#define R500_RS_INST_COL_CN_WRITE_FBUFFER		(2 << 16)
+#define R500_RS_INST_COL_CN_WRITE_BACKFACE		(3 << 16)
+#define R500_RS_INST_COL_COL_ADDR_SHIFT			18
+#define R500_RS_INST_TEX_ADJ				(1 << 25)
+#define R500_RS_INST_W_CN				(1 << 26)
+
+#define R500_US_FC_CTRL					0x4624
+#define R500_US_CODE_ADDR				0x4630
+#define R500_US_CODE_RANGE 				0x4634
+#define R500_US_CODE_OFFSET 				0x4638
+
+#define R500_RS_IP_0					0x4074
+#define R500_RS_IP_PTR_K0				62
+#define R500_RS_IP_PTR_K1 				63
+#define R500_RS_IP_TEX_PTR_S_SHIFT 			0
+#define R500_RS_IP_TEX_PTR_T_SHIFT 			6
+#define R500_RS_IP_TEX_PTR_R_SHIFT 			12
+#define R500_RS_IP_TEX_PTR_Q_SHIFT 			18
+#define R500_RS_IP_COL_PTR_SHIFT 			24
+#define R500_RS_IP_COL_FMT_SHIFT 			27
+#define R500_RS_IP_COL_FMT_RGBA				(0<<27)
+#define R500_RS_IP_OFFSET_EN 				(1 << 31)
+
+
 #endif