diff options
| author | George Wu <geo@flood.OCF.Berkeley.EDU> | 2007-12-17 10:55:36 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2007-12-17 10:55:36 +1000 |
| commit | 79a375dbc7f323e2f551490a35f44ec36bed877c (patch) | |
| tree | e62885650a2356968b6d9516ffcc1164bd6feae6 | |
| parent | bc213ee723a45f2c396b4ed211a50f7642349973 (diff) | |
r600: might as well fix VT for R600
| -rw-r--r-- | src/radeon_driver.c | 32 | ||||
| -rw-r--r-- | src/radeon_reg.h | 15 |
2 files changed, 33 insertions, 14 deletions
diff --git a/src/radeon_driver.c b/src/radeon_driver.c index 16d758ba..ac307ab7 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -5647,11 +5647,18 @@ void avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) state->tmds2.source_select = INREG(AVIVO_LVTMA_SOURCE_SELECT); state->tmds2.bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL); state->tmds2.data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION); - state->tmds2.transmitter_enable = INREG(AVIVO_LVTMA_TRANSMITTER_ENABLE); - state->tmds2.transmitter_cntl = INREG(AVIVO_LVTMA_TRANSMITTER_CONTROL); - state->lvtma_pwrseq_cntl = INREG(AVIVO_LVTMA_PWRSEQ_CNTL); - state->lvtma_pwrseq_state = INREG(AVIVO_LVTMA_PWRSEQ_STATE); + if (info->ChipFamily >= CHIP_FAMILY_R600) { + state->tmds2.transmitter_enable = INREG(R600_LVTMA_TRANSMITTER_ENABLE); + state->tmds2.transmitter_cntl = INREG(R600_LVTMA_TRANSMITTER_CONTROL); + state->lvtma_pwrseq_cntl = INREG(R600_LVTMA_PWRSEQ_CNTL); + state->lvtma_pwrseq_state = INREG(R600_LVTMA_PWRSEQ_STATE); + } else { + state->tmds2.transmitter_enable = INREG(R500_LVTMA_TRANSMITTER_ENABLE); + state->tmds2.transmitter_cntl = INREG(R500_LVTMA_TRANSMITTER_CONTROL); + state->lvtma_pwrseq_cntl = INREG(R500_LVTMA_PWRSEQ_CNTL); + state->lvtma_pwrseq_state = INREG(R500_LVTMA_PWRSEQ_STATE); + } if (state->crtc1.control & AVIVO_CRTC_EN) info->crtc_on = TRUE; @@ -5792,12 +5799,19 @@ void avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(AVIVO_LVTMA_CNTL, state->tmds2.cntl); OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, state->tmds2.bit_depth_cntl); OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2.data_sync); - OUTREG(AVIVO_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable); - OUTREG(AVIVO_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl); OUTREG(AVIVO_LVTMA_SOURCE_SELECT, state->tmds2.source_select); - - OUTREG(AVIVO_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl); - OUTREG(AVIVO_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state); + + if (info->ChipFamily >= CHIP_FAMILY_R600) { + OUTREG(R600_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable); + OUTREG(R600_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl); + OUTREG(R600_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl); + OUTREG(R600_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state); + } else { + OUTREG(R500_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable); + OUTREG(R500_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl); + OUTREG(R500_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl); + OUTREG(R500_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state); + } OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); diff --git a/src/radeon_reg.h b/src/radeon_reg.h index e7ef9324..56eb7e91 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -3606,9 +3606,11 @@ #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) -#define AVIVO_LVTMA_CLOCK_ENABLE 0x7b00 +#define R500_LVTMA_CLOCK_ENABLE 0x7b00 +#define R600_LVTMA_CLOCK_ENABLE 0x7b04 -#define AVIVO_LVTMA_TRANSMITTER_ENABLE 0x7b04 +#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 +#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) @@ -3621,7 +3623,8 @@ # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) -#define AVIVO_LVTMA_TRANSMITTER_CONTROL 0x7b10 +#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 +#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) @@ -3637,7 +3640,8 @@ # define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) -#define AVIVO_LVTMA_PWRSEQ_CNTL 0x7af0 +#define R500_LVTMA_PWRSEQ_CNTL 0x7af0 +#define R600_LVTMA_PWRSEQ_CNTL 0x7af4 # define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) # define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) # define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) @@ -3652,7 +3656,8 @@ # define AVIVO_LVTMA_BLON_OVRD (1 << 25) # define AVIVO_LVTMA_BLON_POL (1 << 26) -#define AVIVO_LVTMA_PWRSEQ_STATE 0x7af4 +#define R500_LVTMA_PWRSEQ_STATE 0x7af4 +#define R600_LVTMA_PWRSEQ_STATE 0x7af8 # define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) # define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) # define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) |