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authorAlex Deucher <alex@botch2.(none)>2007-09-18 20:12:21 -0400
committerAlex Deucher <alex@botch2.(none)>2007-09-18 20:12:21 -0400
commit8ae69c496eba701e744cca0605f73242673f7b3f (patch)
tree74c0d3831642fda8142ee73a86fe98cf4cf94a27
parent8a84dc8ee260716026fa661a6dced2000621efa2 (diff)
RADEON: adjust pll restore
some chips seem to be pickier than others. fixes bug 12467
-rw-r--r--src/radeon_crtc.c1
-rw-r--r--src/radeon_driver.c12
2 files changed, 7 insertions, 6 deletions
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 47e46f38..042d14bf 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -862,6 +862,7 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
case 1:
RADEONAdjustCrtc2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output);
RADEONAdjustPLL2RegistersForTV(pScrn, &info->ModeReg, adjusted_mode, output);
+ update_tv_routing = TRUE;
break;
}
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 4c3a6918..8a113fdd 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4679,10 +4679,10 @@ void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
usleep(50000); /* Let the clock to lock */
- /* OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL,
+ OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL,
RADEON_VCLK_SRC_SEL_PPLLCLK,
- ~(RADEON_VCLK_SRC_SEL_MASK));*/
- OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl);
+ ~(RADEON_VCLK_SRC_SEL_MASK));
+ /*OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl);*/
ErrorF("finished PLL1\n");
@@ -4753,10 +4753,10 @@ void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
usleep(5000); /* Let the clock to lock */
- /*OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL,
+ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL,
RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
- ~(RADEON_PIX2CLK_SRC_SEL_MASK));*/
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl);
+ ~(RADEON_PIX2CLK_SRC_SEL_MASK));
+ /*OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl);*/
ErrorF("finished PLL2\n");