diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2009-10-27 11:55:20 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2009-10-27 11:55:20 -0400 |
| commit | 19b4f5f9b647cd470616b8ec1d34f1e4afa357ad (patch) | |
| tree | ea11d0a171075de8983a339a66ab7260525b8b35 /src/atombios_crtc.c | |
| parent | 5a0019126a57138ee506d9a66738c9e8b75cbb96 (diff) | |
ATOM: fix up DVO for DCE 3.x
AdjustDisplayPll takes care of this for us.
Diffstat (limited to 'src/atombios_crtc.c')
| -rw-r--r-- | src/atombios_crtc.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c index fb7728fa..6c80ea6f 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -328,8 +328,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) xf86OutputPtr output = xf86_config->output[i]; if (output->crtc == crtc) { radeon_encoder = radeon_get_encoder(output); - /* DVO seems to want 2x pixel clock */ - if (radeon_encoder && (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) + /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ + /* AdjustDisplayPll handles this on DCE3.x */ + if (radeon_encoder && + (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) && + !IS_DCE3_VARIANT) sclock *= 2; } } |