diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2010-04-13 11:08:59 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2010-04-13 11:08:59 -0400 |
| commit | 22a46dddd375b2b9399e12fdf168fa5292ff17a4 (patch) | |
| tree | 8227b869aad03913f3add76fde3d8ad69c64174b /src/atombios_crtc.c | |
| parent | c1b817c45477c21234abaaebe78feb7ea4fd92b1 (diff) | |
radeon: add support for pll algo selection
tv-out on atom systems is very particular about it's
dividers. force it to use the old algo.
Should fix fdo bug 27593.
Diffstat (limited to 'src/atombios_crtc.c')
| -rw-r--r-- | src/atombios_crtc.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c index 1d86643b..6f083b48 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -458,6 +458,19 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) unsigned char *space; memset(&spc_param, 0, sizeof(spc_param)); + + if (IS_AVIVO_VARIANT) { + if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, TRUE)) + radeon_crtc->pll_algo = RADEON_PLL_NEW; + else + radeon_crtc->pll_algo = RADEON_PLL_OLD; + } else { + if (xf86ReturnOptValBool(info->Options, OPTION_NEW_PLL, FALSE)) + radeon_crtc->pll_algo = RADEON_PLL_NEW; + else + radeon_crtc->pll_algo = RADEON_PLL_OLD; + } + if (IS_AVIVO_VARIANT) { if ((info->ChipFamily == CHIP_FAMILY_RS600) || (info->ChipFamily == CHIP_FAMILY_RS690) || @@ -471,6 +484,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) for (i = 0; i < xf86_config->num_output; i++) { xf86OutputPtr output = xf86_config->output[i]; if (output->crtc == crtc) { + radeon_output = output->driver_private; radeon_encoder = radeon_get_encoder(output); /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ /* AdjustDisplayPll handles this on DCE3.x */ @@ -478,6 +492,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) && !IS_DCE3_VARIANT) sclock *= 2; + if (radeon_output->active_device & + (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) { + pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; + radeon_crtc->pll_algo = RADEON_PLL_OLD; + } } } @@ -614,7 +633,8 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) } } - RADEONComputePLL(pScrn, &info->pll, sclock, &temp, &fb_div, &frac_fb_div, &ref_div, &post_div, pll_flags); + RADEONComputePLL(crtc, &info->pll, sclock, &temp, + &fb_div, &frac_fb_div, &ref_div, &post_div, pll_flags); sclock = temp; /* 10 khz */ xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO, |