diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2009-08-19 13:29:04 -0400 |
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committer | Alex Deucher <alexdeucher@gmail.com> | 2009-08-19 13:30:37 -0400 |
commit | b1b77a4d6fb7404af9568644e1a8e050fdfa956e (patch) | |
tree | 4b50834355966d710c1ad8ecd938c8d71afee95e /src/atombios_crtc.c | |
parent | 72e0d1b2cb11a67b8e4be4c74913ee44dc051c5b (diff) |
rs600: add support for DisplayPriority HIGH
Still haven't implemented the actual watermark
calculation, but this forces the display requests
to urgent if the user specifies DisplayPriority HIGH.
Diffstat (limited to 'src/atombios_crtc.c')
-rw-r--r-- | src/atombios_crtc.c | 32 |
1 files changed, 30 insertions, 2 deletions
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c index 176efa65..341deb42 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -767,9 +767,37 @@ RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn, OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split); #endif - // fixme - if (info->ChipFamily == CHIP_FAMILY_RS600) + /* fixme + * Still need to implement the actual watermark calculation + * for rs600. This just allows us to force high display + * priority. + */ + if (info->ChipFamily == CHIP_FAMILY_RS600) { + if (info->DispPriority == 2) { + uint32_t priority_cnt; + + if (mode1) { + priority_cnt = INREG(AVIVO_D1MODE_PRIORITY_A_CNT); + priority_cnt |= AVIVO_DxMODE_PRIORITY_ALWAYS_ON; + OUTREG(AVIVO_D1MODE_PRIORITY_A_CNT, priority_cnt); + + priority_cnt = INREG(AVIVO_D1MODE_PRIORITY_B_CNT); + priority_cnt |= AVIVO_DxMODE_PRIORITY_ALWAYS_ON; + OUTREG(AVIVO_D1MODE_PRIORITY_B_CNT, priority_cnt); + } + + if (mode2) { + priority_cnt = INREG(AVIVO_D2MODE_PRIORITY_A_CNT); + priority_cnt |= AVIVO_DxMODE_PRIORITY_ALWAYS_ON; + OUTREG(AVIVO_D2MODE_PRIORITY_A_CNT, priority_cnt); + + priority_cnt = INREG(AVIVO_D2MODE_PRIORITY_B_CNT); + priority_cnt |= AVIVO_DxMODE_PRIORITY_ALWAYS_ON; + OUTREG(AVIVO_D2MODE_PRIORITY_B_CNT, priority_cnt); + } + } return; + } /* IGP bandwidth - get from integrated systems table * SYSTEM_MEMORY_BANDWIDTH (Mbyte/s) = SYSTEM_MEMORY_CLOCK (MHz) * (1+DDR) * 8 * EFF * Num of channels |