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authorAlex Deucher <alex@samba.(none)>2007-12-12 22:18:37 -0500
committerAlex Deucher <alex@samba.(none)>2007-12-12 22:18:37 -0500
commitf2b2e0804183b52d9d3f56ad85b3552ece76c544 (patch)
treec724cb40c8c2b54cd88f814dc9f597a5e0fbd8d1 /src/atombios_crtc.c
parent372bf41818fdafc6a9d2914aee3a8e359f668f02 (diff)
RADEON: fix rotation on avivo chips
There are still some issues, but this is better than before.
Diffstat (limited to 'src/atombios_crtc.c')
-rw-r--r--src/atombios_crtc.c36
1 files changed, 30 insertions, 6 deletions
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 3c61ef78..5b091072 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -238,7 +238,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
void *ptr;
AtomBiosArgRec data;
- unsigned char *space;
+ unsigned char *space;
RADEONSavePtr save = info->ModeReg;
if (IS_AVIVO_VARIANT) {
@@ -383,7 +383,8 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
default:
FatalError("Unsupported screen depth: %d\n", xf86GetDepth());
}
- if (info->tilingEnabled) {
+
+ if (info->tilingEnabled && (crtc->rotatedData == NULL)) {
radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
}
@@ -394,24 +395,47 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
/* setup fb format and location
*/
- OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
- OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
- (mode->HDisplay << 16) | mode->VDisplay);
+ if (crtc->rotatedData != NULL) {
+ /* x/y offset is already included */
+ x = 0;
+ y = 0;
+ fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB;
+ }
+
+ /* lock the grph regs */
+ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1GRPH_UPDATE_LOCK);
OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset,
radeon_crtc->fb_format);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
+ OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset,
crtc->scrn->virtualX);
OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset,
crtc->scrn->virtualY);
OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
crtc->scrn->displayWidth);
-
OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
+ /* unlock the grph regs */
+ OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, 0);
+
+ /* lock the mode regs */
+ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK);
+
+ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
+ crtc->scrn->virtualY);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
+ (mode->HDisplay << 16) | mode->VDisplay);
+ /* unlock the mode regs */
+ OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0);
+
}
atombios_crtc_set_pll(crtc, adjusted_mode);