diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2008-08-14 14:49:45 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2008-08-14 14:49:45 -0400 |
| commit | 92ee21df344a989778e37369c7beb3904a00ead6 (patch) | |
| tree | 614c1163751f139fbb4e881889550dbffce8d0ca /src/atombios_crtc.c | |
| parent | 0d5e0347af4322713075193154b8a348de4a0b52 (diff) | |
PLL adjustments
Seems higher dotclocks prefer a higher FB div.
Someone with a lot of should try and find out where
the div sweet spots are for various dotclock ranges.
fixes bug 17125
Diffstat (limited to 'src/atombios_crtc.c')
| -rw-r--r-- | src/atombios_crtc.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c index 70650e12..8f5b40ae 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -225,7 +225,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) if (IS_AVIVO_VARIANT) { uint32_t temp; - pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; + if (mode->Clock > 120000) /* range limits??? */ + pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; + else + pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; + RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, pll_flags); sclock = temp; |