diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2010-02-03 15:22:22 -0500 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2010-02-03 15:22:22 -0500 |
| commit | 8d63d70f7ebaf9d250f0449d3720ef47516c05df (patch) | |
| tree | 19735472a3d360a3c9ff3332dd429432f4375d5b /src/atombios_output.c | |
| parent | ecbc26431914216a8b207e81451282ea07c8b92f (diff) | |
evergreen: use external clock source for DP PHY
DP CRTC clock always comes from DCPLL. This frees
up PPll1/2 for non-DP-mode PHYs and CRTCs
Diffstat (limited to 'src/atombios_output.c')
| -rw-r--r-- | src/atombios_output.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/atombios_output.c b/src/atombios_output.c index 547cd139..61f5373d 100644 --- a/src/atombios_output.c +++ b/src/atombios_output.c @@ -762,11 +762,14 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t if (radeon_output->linkb) disp_data.v3.acConfig.ucLinkSel = 1; - //if (radeon_output->dig_encoder) - // disp_data.v2.acConfig.ucEncoderSel = 1; + if (radeon_output->dig_encoder & 1) + disp_data.v2.acConfig.ucEncoderSel = 1; - // select the PLL - disp_data.v3.acConfig.ucRefClkSource = radeon_output->pll_id; + // select the PLL for the UNIPHY + if (radeon_output->MonType == MT_DP) + disp_data.v3.acConfig.ucRefClkSource = 2; /* ext clk */ + else + disp_data.v3.acConfig.ucRefClkSource = radeon_output->pll_id; switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |