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authorAlex Deucher <alexdeucher@gmail.com>2010-11-17 17:37:25 -0500
committerAlex Deucher <alexdeucher@gmail.com>2010-12-01 20:30:24 -0500
commitfccdca8db34010f566bd068c74cdef0f4a8cb7f5 (patch)
tree0c92849103181f7cfca01fcf8fbc2860f2891dd4 /src/evergreen_exa.c
parent035f7f3ab529ca19b853066792af8a23d08a0f53 (diff)
radeon/kms: allow tiled front buffer on 6xx/7xx
Use UTS/DFS to tile/untile as appropriate for sw access. Also enables pageflipping with tiling enabled.
Diffstat (limited to 'src/evergreen_exa.c')
-rw-r--r--src/evergreen_exa.c21
1 files changed, 14 insertions, 7 deletions
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 89afaff5..7e627734 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -1647,22 +1647,29 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
Bool flush = FALSE;
Bool r;
struct r600_accel_object src_obj, dst_obj;
+ uint32_t tiling_flags = 0, pitch = 0;
if (bpp < 8)
return FALSE;
driver_priv = exaGetPixmapDriverPrivate(pSrc);
+ ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
+ if (ret)
+ ErrorF("radeon_bo_get_tiling failed\n");
+
/* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
copy_src = driver_priv->bo;
copy_pitch = pSrc->devKind;
- if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
- src_domain = radeon_bo_get_src_domain(driver_priv->bo);
- if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
- (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
- src_domain = 0;
- else /* A write may be scheduled */
- flush = TRUE;
+ if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
+ if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
+ src_domain = radeon_bo_get_src_domain(driver_priv->bo);
+ if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
+ (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
+ src_domain = 0;
+ else /* A write may be scheduled */
+ flush = TRUE;
+ }
}
if (!src_domain)