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authorJerome Glisse <jglisse@redhat.com>2011-12-13 11:08:19 -0500
committerJerome Glisse <jglisse@redhat.com>2012-02-06 19:00:37 -0500
commit615033f2b5e3817e335e9d022fc9fdcf8ac8b11a (patch)
treece50a286a4e6b46beaa8c7f2e6ef0c667179aac7 /src/evergreen_state.h
parent36c190671081967bac6fff48aaf66d67b639a48c (diff)
r600-evergreen: use common surface allocator for tiling v11
Use libdrm common surface code so mesa,ddx have same idea about tiling surface and what their pitch should be and the alignment constraint. v2 fix remaining issue add new option to conditionaly enable v3 fix fbcon copy and r600 exa copy path v4 fix non tiled path 2D tiling on GPU >= R600, set it to false as default v5 adapt to pixel/element size split of libdrm/radeon v6 update to properly handle falling back to 1d tiled v6 final fix to tile split value on evergreen and newer v7 fix default array mode on r6xx, fix height alignment issue on evergreen v8 fix tile split value v9 add stencil tile split support, simplify dri2 for stencil with evergreen v10 Try to fix xv path regarding tiling. Adapt to libdrm API change. Try to fix case where there is no surface which means non tiled bo. v11 check for proper libdrm Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Diffstat (limited to 'src/evergreen_state.h')
-rw-r--r--src/evergreen_state.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/evergreen_state.h b/src/evergreen_state.h
index 5fd85f86..5a29f8fc 100644
--- a/src/evergreen_state.h
+++ b/src/evergreen_state.h
@@ -93,6 +93,9 @@ typedef struct {
int blend_enable;
uint32_t blendcntl;
struct radeon_bo *bo;
+#ifdef XF86DRM_MODE
+ struct radeon_surface *surface;
+#endif
} cb_config_t;
/* Shader */
@@ -179,6 +182,9 @@ typedef struct {
int min_lod;
struct radeon_bo *bo;
struct radeon_bo *mip_bo;
+#ifdef XF86DRM_MODE
+ struct radeon_surface *surface;
+#endif
} tex_resource_t;
/* Texture sampler */