diff options
| author | Jiří Paleček <jpalecek@web.de> | 2008-06-23 15:53:58 -0400 |
|---|---|---|
| committer | Alex Deucher <alex@botch2.com> | 2008-06-23 15:53:58 -0400 |
| commit | 72feaa37ea07620f5f2ead438dbc72a1c8883cd3 (patch) | |
| tree | 239935051ab53d1e6a3d2e871626ae9c86399d71 /src/legacy_crtc.c | |
| parent | 9c2f909ea437a63a408d2398ecabe0b378dbb982 (diff) | |
RADEON: PLL tweaks
Patch from Jiří Paleček (see debian bug 465864) with some tweaks
by me.
- abort rather than programming bad dividers if no pll dividers can be found
- improve the pll selection algorithm
- in general, prefer lower ref dividers
I've tested this patch on a wide variety of chips (r1xx-r6xx) and clocks.
Diffstat (limited to 'src/legacy_crtc.c')
| -rw-r--r-- | src/legacy_crtc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c index 747bc6ed..17ae8c44 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c @@ -1730,7 +1730,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, RADEONInfoPtr info = RADEONPTR(pScrn); int i = 0; double dot_clock = 0; - int pll_flags = RADEON_PLL_LEGACY; + int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV; Bool update_tv_routing = FALSE; Bool tilingChanged = FALSE; |