diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2008-12-17 00:59:52 -0500 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2008-12-17 01:02:44 -0500 |
| commit | b2b43905a5385a8bb0b59b8e50952863d8dacb59 (patch) | |
| tree | 566d0e9ea039bd3dddaab16bf399d7914d157048 /src/legacy_output.c | |
| parent | 3754cc23abac99880eda87d06aa42e16081b6c8a (diff) | |
Pre-avivo: fix FP setup
- make sure to clear various shadow timing bits
- crtc1 select bit was set wrong.
- should fix bugs like 19100
Diffstat (limited to 'src/legacy_output.c')
| -rw-r--r-- | src/legacy_output.c | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/src/legacy_output.c b/src/legacy_output.c index e5ddf1f7..f9b0dffb 100644 --- a/src/legacy_output.c +++ b/src/legacy_output.c @@ -947,12 +947,19 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); + save->fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | + RADEON_FP_DFP_SYNC_SEL | + RADEON_FP_CRT_SYNC_SEL | + RADEON_FP_CRTC_LOCK_8DOT | + RADEON_FP_USE_SHADOW_EN | + RADEON_FP_CRTC_USE_SHADOW_VEND | + RADEON_FP_CRT_SYNC_ALT); + if (pScrn->rgbBits == 8) save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ else save->fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ - if (IsPrimary) { if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) { save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; @@ -961,7 +968,7 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, else save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; } else - save->fp_gen_cntl |= RADEON_FP_SEL_CRTC1; + save->fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; } else { if ((IS_R300_VARIANT) || (info->ChipFamily == CHIP_FAMILY_R200)) { save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; @@ -1037,16 +1044,14 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; else save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; - } else { + } else save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; - } } else { if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; - } else { + } else save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; - } } if ((info->ChipFamily == CHIP_FAMILY_RS400) || |