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authorAlex Deucher <alexdeucher@gmail.com>2009-09-01 13:43:00 -0400
committerAlex Deucher <alexdeucher@gmail.com>2009-09-01 13:43:00 -0400
commitc4ab50c5eafca3d04129a72453496eb8afb26b34 (patch)
tree0f0ed29e428e0f3be209c65ce09b430a9ecc4485 /src/legacy_output.c
parent22fbd6476f4b3513378e848affc4dd269e9d4498 (diff)
radeon: add some notes about DVO setup
Diffstat (limited to 'src/legacy_output.c')
-rw-r--r--src/legacy_output.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 7134ee15..73c86b99 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -1216,14 +1216,25 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save,
if ((info->Chipset == PCI_CHIP_RV350_NP) &&
(PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1028) &&
(PCI_SUB_DEVICE_ID(info->PciInfo) == 0x2001))
- save->fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; /* Dell Inspiron 8600 */
+ save->fp2_gen_cntl |= R200_FP2_DVO_CLOCK_MODE_SINGLE; /* Dell Inspiron 8600 */
else
- save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
+ save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R200_FP2_DVO_CLOCK_MODE_SINGLE;
+ }
+
#if 0
- if (mode->Clock > 165000)
+ /* DVO configurations:
+ * SDR single channel (data rate 165 Mhz, port width 12 bits)
+ * DDR single channel (data rate 330 Mhz, port width 12 bits)
+ * SDR dual channel (data rate 330 Mhz, port width 24 bits)
+ * - dual channel is only available on r3xx+
+ */
+ if (info->ChipFamily >= CHIP_FAMILY_R200) {
+ if (sdr)
+ save->fp2_gen_cntl |= R200_FP2_DVO_RATE_SEL_SDR;
+ if (IS_R300_VARIANT && dual channel)
save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;
-#endif
}
+#endif
if (IsPrimary) {
if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) {