diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2010-08-20 16:55:21 -0400 |
---|---|---|
committer | Alex Deucher <alexdeucher@gmail.com> | 2010-08-20 16:55:21 -0400 |
commit | 6930d2c981221757b1e11ef194809f085753a611 (patch) | |
tree | bc0315f106229488603ba9ef009581772fb9bdcc /src/r600_exa.c | |
parent | bdd41fecdb19c83c6c7b793016b61d38065dcd13 (diff) |
Add initial EXA and Xv support for evergreen
Based on the r6xx/r7xx code updated for evergreen.
Still causes GPU hangs in some cases. We haven't
tracked down why yet. Might be related to constant
buffer persistence.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Diffstat (limited to 'src/r600_exa.c')
-rw-r--r-- | src/r600_exa.c | 106 |
1 files changed, 53 insertions, 53 deletions
diff --git a/src/r600_exa.c b/src/r600_exa.c index d6e98ff7..77020870 100644 --- a/src/r600_exa.c +++ b/src/r600_exa.c @@ -43,7 +43,7 @@ /* #define SHOW_VERTEXES */ -uint32_t RADEON_ROP[16] = { +uint32_t R600_ROP[16] = { RADEON_ROP3_ZERO, /* GXclear */ RADEON_ROP3_DSa, /* Gxand */ RADEON_ROP3_SDna, /* GXandReverse */ @@ -211,11 +211,11 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) radeon_vbo_check(pScrn, 16); radeon_cp_start(pScrn); - set_default_state(pScrn, accel_state->ib); + r600_set_default_state(pScrn, accel_state->ib); - set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; @@ -223,7 +223,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) vs_conf.num_gprs = 2; vs_conf.stack_size = 0; vs_conf.bo = accel_state->shaders_bo; - vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); + r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; @@ -233,7 +233,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; - ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM); + r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; @@ -253,7 +253,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) } cb_conf.source_format = 1; cb_conf.blend_clamp = 1; - set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); + r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); /* Render setup */ if (accel_state->planemask & 0x000000ff) @@ -266,7 +266,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) pmask |= 8; /* A */ BEGIN_BATCH(20); EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift)); - EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[accel_state->rop]); + EREG(accel_state->ib, CB_COLOR_CONTROL, R600_ROP[accel_state->rop]); /* Interpolator setup */ /* one unused export from VS (VS_EXPORT_COUNT is zero based, count minus one) */ @@ -312,8 +312,8 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) ps_alu_consts[2] = (float)b / 255; /* B */ ps_alu_consts[3] = (float)a / 255; /* A */ } - set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps, - sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); + r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps, + sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); if (accel_state->vsync) RADEONVlineHelperClear(pScrn); @@ -355,10 +355,10 @@ R600DoneSolid(PixmapPtr pPix) struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->vsync) - cp_wait_vline_sync(pScrn, accel_state->ib, pPix, - accel_state->vline_crtc, - accel_state->vline_y1, - accel_state->vline_y2); + r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix, + accel_state->vline_crtc, + accel_state->vline_y1, + accel_state->vline_y2); r600_finish_op(pScrn, 8); } @@ -383,11 +383,11 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) radeon_vbo_check(pScrn, 16); radeon_cp_start(pScrn); - set_default_state(pScrn, accel_state->ib); + r600_set_default_state(pScrn, accel_state->ib); - set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); /* Shader */ vs_conf.shader_addr = accel_state->vs_mc_addr; @@ -395,7 +395,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) vs_conf.num_gprs = 2; vs_conf.stack_size = 0; vs_conf.bo = accel_state->shaders_bo; - vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); + r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; @@ -405,7 +405,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; - ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM); + r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM); /* Texture */ tex_res.id = 0; @@ -443,7 +443,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; - set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); + r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); tex_samp.id = 0; tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; @@ -453,7 +453,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ - set_tex_sampler (pScrn, accel_state->ib, &tex_samp); + r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; @@ -472,7 +472,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) } cb_conf.source_format = 1; cb_conf.blend_clamp = 1; - set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); + r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); /* Render setup */ if (accel_state->planemask & 0x000000ff) @@ -485,7 +485,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) pmask |= 8; /* A */ BEGIN_BATCH(20); EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift)); - EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[accel_state->rop]); + EREG(accel_state->ib, CB_COLOR_CONTROL, R600_ROP[accel_state->rop]); /* Interpolator setup */ /* export tex coord from VS */ @@ -521,10 +521,10 @@ R600DoCopyVline(PixmapPtr pPix) struct radeon_accel_state *accel_state = info->accel_state; if (accel_state->vsync) - cp_wait_vline_sync(pScrn, accel_state->ib, pPix, - accel_state->vline_crtc, - accel_state->vline_y1, - accel_state->vline_y2); + r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix, + accel_state->vline_crtc, + accel_state->vline_y1, + accel_state->vline_y2); r600_finish_op(pScrn, 16); } @@ -603,7 +603,7 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst, src_obj.height = pSrc->drawable.height; src_obj.bpp = pSrc->drawable.bitsPerPixel; src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; - + dst_obj.width = pDst->drawable.width; dst_obj.height = pDst->drawable.height; dst_obj.bpp = pDst->drawable.bitsPerPixel; @@ -1060,7 +1060,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; - set_tex_resource (pScrn, accel_state->ib, &tex_res, accel_state->src_obj[unit].domain); + r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[unit].domain); tex_samp.id = unit; tex_samp.border_color = SQ_TEX_BORDER_COLOR_TRANS_BLACK; @@ -1102,7 +1102,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, tex_samp.clamp_z = SQ_TEX_WRAP; tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; tex_samp.mip_filter = 0; /* no mipmap */ - set_tex_sampler (pScrn, accel_state->ib, &tex_samp); + r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp); if (pPict->transform != 0) { accel_state->is_transform[unit] = TRUE; @@ -1132,8 +1132,8 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, } /* VS alu constants */ - set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs + (unit * 2), - sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts); + r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs + (unit * 2), + sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts); return TRUE; } @@ -1264,7 +1264,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, if (info->cs) { mask_obj.offset = 0; mask_obj.bo = radeon_get_pixmap_bo(pMask); - } else + } else #endif { mask_obj.offset = exaGetPixmapOffset(pMask) + info->fbLocation + pScrn->fbOffset; @@ -1324,11 +1324,11 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, radeon_cp_start(pScrn); - set_default_state(pScrn, accel_state->ib); + r600_set_default_state(pScrn, accel_state->ib); - set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); - set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_screen_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); + r600_set_window_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); if (!R600TextureSetup(pSrcPicture, pSrc, 0)) { R600IBDiscard(pScrn, accel_state->ib); @@ -1346,11 +1346,11 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, accel_state->is_transform[1] = FALSE; if (pMask) { - set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (1 << 0)); - set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0)); + r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (1 << 0)); + r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (1 << 0)); } else { - set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (0 << 0)); - set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0)); + r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_vs, (0 << 0)); + r600_set_bool_consts(pScrn, accel_state->ib, SQ_BOOL_CONST_ps, (0 << 0)); } /* Shader */ @@ -1359,7 +1359,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, vs_conf.num_gprs = 3; vs_conf.stack_size = 1; vs_conf.bo = accel_state->shaders_bo; - vs_setup (pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); + r600_vs_setup(pScrn, accel_state->ib, &vs_conf, RADEON_GEM_DOMAIN_VRAM); ps_conf.shader_addr = accel_state->ps_mc_addr; ps_conf.shader_size = accel_state->ps_size; @@ -1369,7 +1369,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, ps_conf.clamp_consts = 0; ps_conf.export_mode = 2; ps_conf.bo = accel_state->shaders_bo; - ps_setup (pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM); + r600_ps_setup(pScrn, accel_state->ib, &ps_conf, RADEON_GEM_DOMAIN_VRAM); cb_conf.id = 0; cb_conf.w = accel_state->dst_obj.pitch; @@ -1405,7 +1405,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, } cb_conf.source_format = 1; cb_conf.blend_clamp = 1; - set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); + r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); BEGIN_BATCH(24); EREG(accel_state->ib, CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift)); @@ -1414,10 +1414,10 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, if (info->ChipFamily == CHIP_FAMILY_R600) { /* no per-MRT blend on R600 */ - EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[3] | (1 << TARGET_BLEND_ENABLE_shift)); + EREG(accel_state->ib, CB_COLOR_CONTROL, R600_ROP[3] | (1 << TARGET_BLEND_ENABLE_shift)); EREG(accel_state->ib, CB_BLEND_CONTROL, blendcntl); } else { - EREG(accel_state->ib, CB_COLOR_CONTROL, (RADEON_ROP[3] | + EREG(accel_state->ib, CB_COLOR_CONTROL, (R600_ROP[3] | (1 << TARGET_BLEND_ENABLE_shift) | PER_MRT_BLEND_bit)); EREG(accel_state->ib, CB_BLEND0_CONTROL, blendcntl); @@ -1542,10 +1542,10 @@ static void R600DoneComposite(PixmapPtr pDst) int vtx_size; if (accel_state->vsync) - cp_wait_vline_sync(pScrn, accel_state->ib, pDst, - accel_state->vline_crtc, - accel_state->vline_y1, - accel_state->vline_y2); + r600_cp_wait_vline_sync(pScrn, accel_state->ib, pDst, + accel_state->vline_crtc, + accel_state->vline_y1, + accel_state->vline_y2); vtx_size = accel_state->msk_pic ? 24 : 16; @@ -1913,7 +1913,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w, src_obj.bpp = bpp; src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; src_obj.bo = radeon_get_pixmap_bo(pSrc); - + dst_obj.pitch = dst_pitch_hw; dst_obj.width = w; dst_obj.height = h; |