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authorAlex Deucher <alexdeucher@gmail.com>2009-10-09 11:07:30 -0400
committerAlex Deucher <alexdeucher@gmail.com>2009-10-09 11:07:30 -0400
commitde55995e82c3875f70b6394fff440d695d062113 (patch)
tree27a08a063c9f6266fcd654a6c1d03f90722ac0a5 /src/r600_exa.c
parenta168caf5349b757873ad89d977772feaa7fb6e58 (diff)
r600 EXA: fix up mask reg mixup
Diffstat (limited to 'src/r600_exa.c')
-rw-r--r--src/r600_exa.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 47f1624e..a2ce5c9f 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -284,7 +284,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
if (pm & 0xff000000)
pmask |= 8; /* A */
BEGIN_BATCH(6);
- EREG(accel_state->ib, CB_SHADER_MASK, (pmask << OUTPUT0_ENABLE_shift));
+ EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[alu]);
END_BATCH();
@@ -611,7 +611,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
if (planemask & 0xff000000)
pmask |= 8; /* A */
BEGIN_BATCH(6);
- EREG(accel_state->ib, CB_SHADER_MASK, (pmask << OUTPUT0_ENABLE_shift));
+ EREG(accel_state->ib, CB_TARGET_MASK, (pmask << TARGET0_ENABLE_shift));
EREG(accel_state->ib, CB_COLOR_CONTROL, RADEON_ROP[rop]);
END_BATCH();
@@ -1801,7 +1801,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
ps_setup (pScrn, accel_state->ib, &ps_conf);
BEGIN_BATCH(9);
- EREG(accel_state->ib, CB_SHADER_MASK, (0xf << OUTPUT0_ENABLE_shift));
+ EREG(accel_state->ib, CB_TARGET_MASK, (0xf << TARGET0_ENABLE_shift));
blendcntl = R600GetBlendCntl(op, pMaskPicture, pDstPicture->format);