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authorAlex Deucher <alexdeucher@gmail.com>2009-02-09 14:13:16 -0500
committerAlex Deucher <alexdeucher@gmail.com>2009-02-09 14:13:16 -0500
commite85b7a1c5948b5123eddf9dfbb9e002d74fbe9fb (patch)
tree7ad1c25b02ac9d4fc970b284c14b9d5fa073e4e1 /src/r600_textured_videofuncs.c
parent2a893bac1faffd28dce6d9a9693108196c71e6d3 (diff)
R6xx/R7xx Xv: fix cache flush buffer size for planar
Diffstat (limited to 'src/r600_textured_videofuncs.c')
-rw-r--r--src/r600_textured_videofuncs.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index 42a5d68d..24bba07d 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -205,7 +205,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
uv_offset = (uv_offset + 255) & ~255;
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
- accel_state->src_size[0] / 2,
+ accel_state->src_size[0] / 4,
accel_state->src_mc_addr[0] + uv_offset);
tex_res.id = 1;
@@ -232,7 +232,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
uv_offset = (uv_offset + 255) & ~255;
cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit,
- accel_state->src_size[0] / 2,
+ accel_state->src_size[0] / 4,
accel_state->src_mc_addr[0] + uv_offset);
tex_res.id = 2;