diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2009-03-01 22:30:31 -0500 |
---|---|---|
committer | Alex Deucher <alexdeucher@gmail.com> | 2009-03-01 22:30:31 -0500 |
commit | a8e631c1b1c9b46602aeca66f8e7e68154d0bfc8 (patch) | |
tree | 1f14b38a0934abb872a6c6d663ff19b1468bf105 /src/r600_textured_videofuncs.c | |
parent | 528061d51bb4248d6fabec9579dead32a730467a (diff) |
R6xx/R7xx: code cleanups
Diffstat (limited to 'src/r600_textured_videofuncs.c')
-rw-r--r-- | src/r600_textured_videofuncs.c | 68 |
1 files changed, 33 insertions, 35 deletions
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c index 0932bc88..bf98ec78 100644 --- a/src/r600_textured_videofuncs.c +++ b/src/r600_textured_videofuncs.c @@ -117,9 +117,9 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) int uv_offset; static float ps_alu_consts[] = { - 1.0, 0.0, 1.4020, 0, // r - c[0] - 1.0, -0.34414, -0.71414, 0, // g - c[1] - 1.0, 1.7720, 0.0, 0, // b - c[2] + 1.0, 0.0, 1.4020, 0, /* r - c[0] */ + 1.0, -0.34414, -0.71414, 0, /* g - c[1] */ + 1.0, 1.7720, 0.0, 0, /* b - c[2] */ /* Constants for undoing Y'CbCr scaling * - Y' is scaled from 16:235 * - Cb/Cr are scaled from 16:240 @@ -138,7 +138,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) accel_state->dst_pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8); accel_state->src_pitch[0] = pPriv->src_pitch; - // bad pitch + /* bad pitch */ if (accel_state->src_pitch[0] & 7) return; if (accel_state->dst_pitch & 7) @@ -157,8 +157,6 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) /* Init */ start_3d(pScrn, accel_state->ib); - //cp_set_surface_sync(pScrn, accel_state->ib); - set_default_state(pScrn, accel_state->ib); /* Scissor / viewport */ @@ -208,7 +206,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) ps_conf.export_mode = 2; ps_setup (pScrn, accel_state->ib, &ps_conf); - // PS alu constants + /* PS alu constants */ set_alu_consts(pScrn, accel_state->ib, 0, sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); /* Texture */ @@ -222,7 +220,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0], accel_state->src_mc_addr[0]); - // Y texture + /* Y texture */ tex_res.id = 0; tex_res.w = pPriv->w; tex_res.h = pPriv->h; @@ -233,7 +231,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.mip_base = accel_state->src_mc_addr[0]; tex_res.format = FMT_8; - tex_res.dst_sel_x = SQ_SEL_X; //Y + tex_res.dst_sel_x = SQ_SEL_X; /* Y */ tex_res.dst_sel_y = SQ_SEL_1; tex_res.dst_sel_z = SQ_SEL_1; tex_res.dst_sel_w = SQ_SEL_1; @@ -245,13 +243,13 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.interlaced = 0; set_tex_resource (pScrn, accel_state->ib, &tex_res); - // Y sampler + /* Y sampler */ tex_samp.id = 0; tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_z = SQ_TEX_WRAP; - // xxx: switch to bicubic + /* xxx: switch to bicubic */ tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; @@ -259,7 +257,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_samp.mip_filter = 0; /* no mipmap */ set_tex_sampler (pScrn, accel_state->ib, &tex_samp); - // U or V texture + /* U or V texture */ uv_offset = accel_state->src_pitch[0] * pPriv->h; uv_offset = (uv_offset + 255) & ~255; @@ -272,21 +270,21 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.w = pPriv->w >> 1; tex_res.h = pPriv->h >> 1; tex_res.pitch = accel_state->src_pitch[0] >> 1; - tex_res.dst_sel_x = SQ_SEL_X; //V or U + tex_res.dst_sel_x = SQ_SEL_X; /* V or U */ tex_res.dst_sel_y = SQ_SEL_1; tex_res.dst_sel_z = SQ_SEL_1; tex_res.dst_sel_w = SQ_SEL_1; tex_res.interlaced = 0; - // XXX tex bases need to be 256B aligned + tex_res.base = accel_state->src_mc_addr[0] + uv_offset; tex_res.mip_base = accel_state->src_mc_addr[0] + uv_offset; set_tex_resource (pScrn, accel_state->ib, &tex_res); - // U or V sampler + /* U or V sampler */ tex_samp.id = 1; set_tex_sampler (pScrn, accel_state->ib, &tex_samp); - // U or V texture + /* U or V texture */ uv_offset += ((accel_state->src_pitch[0] >> 1) * (pPriv->h >> 1)); uv_offset = (uv_offset + 255) & ~255; @@ -299,17 +297,17 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.w = pPriv->w >> 1; tex_res.h = pPriv->h >> 1; tex_res.pitch = accel_state->src_pitch[0] >> 1; - tex_res.dst_sel_x = SQ_SEL_X; //V or U + tex_res.dst_sel_x = SQ_SEL_X; /* V or U */ tex_res.dst_sel_y = SQ_SEL_1; tex_res.dst_sel_z = SQ_SEL_1; tex_res.dst_sel_w = SQ_SEL_1; tex_res.interlaced = 0; - // XXX tex bases need to be 256B aligned + tex_res.base = accel_state->src_mc_addr[0] + uv_offset; tex_res.mip_base = accel_state->src_mc_addr[0] + uv_offset; set_tex_resource (pScrn, accel_state->ib, &tex_res); - // UV sampler + /* UV sampler */ tex_samp.id = 2; set_tex_sampler (pScrn, accel_state->ib, &tex_samp); break; @@ -323,7 +321,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) cp_set_surface_sync(pScrn, accel_state->ib, TC_ACTION_ENA_bit, accel_state->src_size[0], accel_state->src_mc_addr[0]); - // Y texture + /* Y texture */ tex_res.id = 0; tex_res.w = pPriv->w; tex_res.h = pPriv->h; @@ -335,9 +333,9 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.format = FMT_8_8; if (pPriv->id == FOURCC_UYVY) - tex_res.dst_sel_x = SQ_SEL_Y; //Y + tex_res.dst_sel_x = SQ_SEL_Y; /* Y */ else - tex_res.dst_sel_x = SQ_SEL_X; //Y + tex_res.dst_sel_x = SQ_SEL_X; /* Y */ tex_res.dst_sel_y = SQ_SEL_1; tex_res.dst_sel_z = SQ_SEL_1; tex_res.dst_sel_w = SQ_SEL_1; @@ -349,13 +347,13 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.interlaced = 0; set_tex_resource (pScrn, accel_state->ib, &tex_res); - // Y sampler + /* Y sampler */ tex_samp.id = 0; tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; tex_samp.clamp_z = SQ_TEX_WRAP; - // xxx: switch to bicubic + /* xxx: switch to bicubic */ tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; @@ -363,28 +361,28 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_samp.mip_filter = 0; /* no mipmap */ set_tex_sampler (pScrn, accel_state->ib, &tex_samp); - // UV texture + /* UV texture */ tex_res.id = 1; tex_res.format = FMT_8_8_8_8; tex_res.w = pPriv->w >> 1; tex_res.h = pPriv->h; tex_res.pitch = accel_state->src_pitch[0] >> 2; if (pPriv->id == FOURCC_UYVY) { - tex_res.dst_sel_x = SQ_SEL_X; //V - tex_res.dst_sel_y = SQ_SEL_Z; //U + tex_res.dst_sel_x = SQ_SEL_X; /* V */ + tex_res.dst_sel_y = SQ_SEL_Z; /* U */ } else { - tex_res.dst_sel_x = SQ_SEL_Y; //V - tex_res.dst_sel_y = SQ_SEL_W; //U + tex_res.dst_sel_x = SQ_SEL_Y; /* V */ + tex_res.dst_sel_y = SQ_SEL_W; /* U */ } tex_res.dst_sel_z = SQ_SEL_1; tex_res.dst_sel_w = SQ_SEL_1; tex_res.interlaced = 0; - // XXX tex bases need to be 256B aligned + tex_res.base = accel_state->src_mc_addr[0]; tex_res.mip_base = accel_state->src_mc_addr[0]; set_tex_resource (pScrn, accel_state->ib, &tex_res); - // UV sampler + /* UV sampler */ tex_samp.id = 1; set_tex_sampler (pScrn, accel_state->ib, &tex_samp); break; @@ -407,15 +405,15 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) case 16: if (pPixmap->drawable.depth == 15) { cb_conf.format = COLOR_1_5_5_5; - cb_conf.comp_swap = 1; //ARGB + cb_conf.comp_swap = 1; /* ARGB */ } else { cb_conf.format = COLOR_5_6_5; - cb_conf.comp_swap = 2; //RGB + cb_conf.comp_swap = 2; /* RGB */ } break; case 32: cb_conf.format = COLOR_8_8_8_8; - cb_conf.comp_swap = 1; //ARGB + cb_conf.comp_swap = 1; /* ARGB */ break; default: return; @@ -432,7 +430,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */ /* Interpolator setup */ - // export tex coords from VS + /* export tex coords from VS */ EREG(accel_state->ib, SPI_VS_OUT_CONFIG, ((1 - 1) << VS_EXPORT_COUNT_shift)); EREG(accel_state->ib, SPI_VS_OUT_ID_0, (0 << SEMANTIC_0_shift)); |