diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2010-02-04 10:52:14 -0500 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2010-02-04 10:52:14 -0500 |
| commit | 76eea5e02776f7beeb8f4491a374bd36792eda92 (patch) | |
| tree | f1f4a7343175e1f9495c771bac2b245e668e6a85 /src/r6xx_accel.c | |
| parent | 8d63d70f7ebaf9d250f0449d3720ef47516c05df (diff) | |
r600: reduce number of cache flushes
We don't need to flush so often. Next step
would be to move the flushing to the drm and only
flush after each command buffer rather than each
draw.
Diffstat (limited to 'src/r6xx_accel.c')
| -rw-r--r-- | src/r6xx_accel.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c index 7a225e55..c0be4d53 100644 --- a/src/r6xx_accel.c +++ b/src/r6xx_accel.c @@ -159,7 +159,6 @@ start_3d(ScrnInfoPtr pScrn, drmBufPtr ib) E32(ib, 0x80000000); END_BATCH(); - wait_3d_idle_clean (pScrn, ib); } /* @@ -1279,6 +1278,7 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size) draw_auto(pScrn, accel_state->ib, &draw_conf); + /* XXX drm should handle this in fence submit */ wait_3d_idle_clean(pScrn, accel_state->ib); /* sync dst surface */ @@ -1286,8 +1286,6 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size) accel_state->dst_size, accel_state->dst_mc_addr, accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM, 0); - wait_3d_idle_clean(pScrn, accel_state->ib); - accel_state->vb_start_op = -1; accel_state->ib_reset_op = 0; |