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authorRoland Scheidegger <rscheidegger_lists@hispeed.ch>2005-01-26 18:23:41 +0000
committerRoland Scheidegger <rscheidegger_lists@hispeed.ch>2005-01-26 18:23:41 +0000
commita2b123f7672ea678290798786ecb408a86d8c683 (patch)
treeb3ee76a2664b7156875b5abb4891d0499e56994a /src/radeon.h
parente0df1e41724cd009fe7c833d2f9555f5d87e3202 (diff)
(Stephane Marchesin, me) Add support for color (framebuffer) tiling.
Convert all XAA accel code to use explicit dst and src offset pitch control to make it work. Use the new drm surface ioctls to set up the tiled surfaces (if dri is enabled).
Diffstat (limited to 'src/radeon.h')
-rw-r--r--src/radeon.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/radeon.h b/src/radeon.h
index 48be2122..20fad258 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -142,6 +142,8 @@ typedef struct {
CARD32 clock_cntl_index;
CARD32 amcgpio_en_reg;
CARD32 amcgpio_mask;
+
+ CARD32 surfaces[8][3];
/* CRTC registers */
CARD32 crtc_gen_cntl;
@@ -367,6 +369,8 @@ typedef struct {
xf86CursorInfoPtr cursor;
unsigned long cursor_start;
unsigned long cursor_end;
+ Bool allowColorTiling;
+ Bool tilingEnabled; /* mirror of sarea->tiling_enabled */
#ifdef ARGB_CURSOR
Bool cursor_argb;
#endif
@@ -654,7 +658,7 @@ extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr);
extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
-extern void RADEONSelectBuffer(ScrnInfoPtr pScrn, int buffer);
+extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn);
extern Bool RADEONAccelInit(ScreenPtr pScreen);
extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a);