XFree86 4.3.99.16 Bring the tree up to date for the Cygwin folksxf86-4_3_99_16

1 files changed, 54 insertions, 46 deletions

diff --git a/src/radeon.h b/src/radeon.h
index 81e0db7b..ded0bde1 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.37 2003/02/23 23:28:48 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.44 2003/11/10 18:41:21 tsi Exp $ */
 /*
  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  *                VA Linux Systems Inc., Fremont, California.
@@ -72,8 +72,8 @@
 #define RADEON_MMIOSIZE   0x80000
 
 #define RADEON_VBIOS_SIZE 0x00010000
-#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX 
-				   * Need to comfirm this is not used 
+#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX
+				   * Need to comfirm this is not used
 				   * for something else.
 				   */
 
@@ -94,20 +94,6 @@ do {									\
 #define RADEONPTR(pScrn)      ((RADEONInfoPtr)(pScrn)->driverPrivate)
 
 typedef struct {
-				/* All values in XCLKS    */
-    int               ML;            /* Memory Read Latency    */
-    int               MB;            /* Memory Burst Length    */
-    int               Trcd;          /* RAS to CAS delay       */
-    int               Trp;           /* RAS percentage         */
-    int               Twr;           /* Write Recovery         */
-    int               CL;            /* CAS Latency            */
-    int               Tr2w;          /* Read to Write Delay    */
-    int               Rloop;         /* Loop Latency           */
-    int               Rloop_fudge;   /* Add to ML to get Rloop */
-    char              *name;
-} RADEONRAMRec, *RADEONRAMPtr;
-
-typedef struct {
 				/* Common registers */
     CARD32            ovr_clr;
     CARD32            ovr_wid_left_right;
@@ -123,7 +109,7 @@ typedef struct {
     CARD32            cap1_trig_cntl;
     CARD32            bus_cntl;
     CARD32            surface_cntl;
-
+    CARD32            bios_5_scratch;
 				/* Other registers to save for VT switches */
     CARD32            dp_datatype;
     CARD32            rbbm_soft_reset;
@@ -142,6 +128,9 @@ typedef struct {
     CARD32            crtc_offset;
     CARD32            crtc_offset_cntl;
     CARD32            crtc_pitch;
+    CARD32            disp_merge_cntl;
+    CARD32            grph_buffer_cntl;
+    CARD32            crtc_more_cntl;
 
 				/* CRTC2 registers */
     CARD32            crtc2_gen_cntl;
@@ -149,6 +138,8 @@ typedef struct {
     CARD32            dac2_cntl;
     CARD32            disp_output_cntl;
     CARD32            disp_hw_debug;
+    CARD32            disp2_merge_cntl;
+    CARD32            grph2_buffer_cntl;
     CARD32            crtc2_h_total_disp;
     CARD32            crtc2_h_sync_strt_wid;
     CARD32            crtc2_v_total_disp;
@@ -171,6 +162,7 @@ typedef struct {
     CARD32            lvds_gen_cntl;
     CARD32            lvds_pll_cntl;
     CARD32            tmds_pll_cntl;
+    CARD32            tmds_transmitter_cntl;
 
 				/* Computed values for PLL */
     CARD32            dot_clock_freq;
@@ -179,8 +171,8 @@ typedef struct {
     int               post_div;
 
 				/* PLL registers */
-    CARD32            ppll_ref_div;
-    CARD32            ppll_div_3;
+    unsigned          ppll_ref_div;
+    unsigned          ppll_div_3;
     CARD32            htotal_cntl;
 
 				/* Computed values for PLL2 */
@@ -245,20 +237,27 @@ typedef enum {
 typedef enum {
     CHIP_FAMILY_UNKNOW,
     CHIP_FAMILY_LEGACY,
-    CHIP_FAMILY_R128,
-    CHIP_FAMILY_M3,
     CHIP_FAMILY_RADEON,
-    CHIP_FAMILY_VE,
-    CHIP_FAMILY_M6,
+    CHIP_FAMILY_RV100,
+    CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
     CHIP_FAMILY_RV200,
-    CHIP_FAMILY_M7,
+    CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
     CHIP_FAMILY_R200,
     CHIP_FAMILY_RV250,
-    CHIP_FAMILY_M9,
-    CHIP_FAMILY_R300
+    CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
+    CHIP_FAMILY_RV280,
+    CHIP_FAMILY_R300,
+    CHIP_FAMILY_R350,
+    CHIP_FAMILY_RV350,
+    CHIP_FAMILY_LAST
 } RADEONChipFamily;
 
 typedef struct {
+    CARD32 freq;
+    CARD32 value;
+}RADEONTMDSPll;
+
+typedef struct {
     EntityInfoPtr     pEnt;
     pciVideoPtr       PciInfo;
     PCITAG            PciTag;
@@ -285,10 +284,10 @@ typedef struct {
     RADEONDDCType     DDCType;
     RADEONConnectorType ConnectorType;
     Bool              HasCRTC2;         /* All cards except original Radeon  */
+    Bool              IsMobility;       /* Mobile chips for laptops */
+    Bool              IsIGP;            /* IGP chips */
     Bool              IsSecondary;      /* Second Screen                     */
     Bool              IsSwitching;      /* Flag for switching mode           */
-    Bool              IsDell;           /* Dell OEM VE card                  */
-    int               DellType;
     Bool              Clone;            /* Force second head to clone primary*/
     RADEONMonitorType CloneType;
     RADEONDDCType     CloneDDCType;
@@ -299,7 +298,7 @@ typedef struct {
     Bool              OverlayOnCRTC2;
     Bool              PanelOff;         /* Force panel (LCD/DFP) off         */
     int               FPBIOSstart;      /* Start of the flat panel info      */
-    Bool              ddc_mode;         /* Validate mode by matching exactly  
+    Bool              ddc_mode;         /* Validate mode by matching exactly
 					 * the modes supported in DDC data
 					 */
     Bool              R300CGWorkaround;
@@ -315,7 +314,10 @@ typedef struct {
     int               VBlank;
     int               PanelPwrDly;
     int               DotClock;
-
+    int               RefDivider;
+    int               FeedbackDivider;
+    int               PostDivider;
+    Bool              UseBiosDividers;
 				/* EDID data using DDC interface */
     Bool              ddc_bios;
     Bool              ddc1;
@@ -324,7 +326,12 @@ typedef struct {
     CARD32            DDCReg;
 
     RADEONPLLRec      pll;
-    RADEONRAMPtr      ram;
+    RADEONTMDSPll     tmds_pll[4];
+    int               RamWidth;
+    float	      sclk;		/* in MHz */
+    float	      mclk;		/* in MHz */
+    Bool	      IsDDR;
+    int               DispPriority;
 
     RADEONSaveRec     SavedReg;         /* Original (text) mode              */
     RADEONSaveRec     ModeReg;          /* Current mode                      */
@@ -420,9 +427,9 @@ typedef struct {
     Bool              have3DWindows;    /* Are there any 3d clients? */
     int               drmMinor;
 
-    drmSize           agpSize;
+    drmSize           gartSize;
     drmHandle         agpMemHandle;     /* Handle from drmAgpAlloc */
-    unsigned long     agpOffset;
+    unsigned long     gartOffset;
     unsigned char     *AGP;             /* Map */
     int               agpMode;
     int               agpFastWrite;
@@ -437,20 +444,20 @@ typedef struct {
     int               CPusecTimeout;    /* CP timeout in usecs */
 
 				/* CP ring buffer data */
-    unsigned long     ringStart;        /* Offset into AGP space */
+    unsigned long     ringStart;        /* Offset into GART space */
     drmHandle         ringHandle;       /* Handle from drmAddMap */
     drmSize           ringMapSize;      /* Size of map */
     int               ringSize;         /* Size of ring (in MB) */
     unsigned char     *ring;            /* Map */
     int               ringSizeLog2QW;
 
-    unsigned long     ringReadOffset;   /* Offset into AGP space */
+    unsigned long     ringReadOffset;   /* Offset into GART space */
     drmHandle         ringReadPtrHandle; /* Handle from drmAddMap */
     drmSize           ringReadMapSize;  /* Size of map */
     unsigned char     *ringReadPtr;     /* Map */
 
 				/* CP vertex/indirect buffer data */
-    unsigned long     bufStart;         /* Offset into AGP space */
+    unsigned long     bufStart;         /* Offset into GART space */
     drmHandle         bufHandle;        /* Handle from drmAddMap */
     drmSize           bufMapSize;       /* Size of map */
     int               bufSize;          /* Size of buffers (in MB) */
@@ -458,13 +465,13 @@ typedef struct {
     int               bufNumBufs;       /* Number of buffers */
     drmBufMapPtr      buffers;          /* Buffer map */
 
-				/* CP AGP Texture data */
-    unsigned long     agpTexStart;      /* Offset into AGP space */
-    drmHandle         agpTexHandle;     /* Handle from drmAddMap */
-    drmSize           agpTexMapSize;    /* Size of map */
-    int               agpTexSize;       /* Size of AGP tex space (in MB) */
-    unsigned char     *agpTex;          /* Map */
-    int               log2AGPTexGran;
+				/* CP GART Texture data */
+    unsigned long     gartTexStart;      /* Offset into GART space */
+    drmHandle         gartTexHandle;     /* Handle from drmAddMap */
+    drmSize           gartTexMapSize;    /* Size of map */
+    int               gartTexSize;       /* Size of GART tex space (in MB) */
+    unsigned char     *gartTex;          /* Map */
+    int               log2GARTTexGran;
 
 				/* CP accleration */
     drmBufPtr         indirectBuffer;
@@ -566,12 +573,13 @@ extern Bool        RADEONDGAInit(ScreenPtr pScreen);
 extern int         RADEONMinBits(int val);
 
 extern void        RADEONInitVideo(ScreenPtr pScreen);
-
+extern void        RADEONResetVideo(ScrnInfoPtr pScrn);
 extern void        R300CGWorkaround(ScrnInfoPtr pScrn);
 
 #ifdef XF86DRI
 extern Bool        RADEONDRIScreenInit(ScreenPtr pScreen);
 extern void        RADEONDRICloseScreen(ScreenPtr pScreen);
+extern void        RADEONDRIResume(ScreenPtr pScreen);
 extern Bool        RADEONDRIFinishScreenInit(ScreenPtr pScreen);
 
 extern drmBufPtr   RADEONCPGetBuffer(ScrnInfoPtr pScrn);
@@ -667,7 +675,7 @@ do {									\
 		   "ADVANCE_RING() start: %d used: %d count: %d\n",	\
 		   info->indirectStart,					\
 		   info->indirectBuffer->used,				\
-		   __count * sizeof(CARD32));				\
+		   __count * (int)sizeof(CARD32));			\
     }									\
     info->indirectBuffer->used += __count * (int)sizeof(CARD32);	\
 } while (0)