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| author | Alex Deucher <alexdeucher@gmail.com> | 2011-04-20 03:10:08 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2011-04-20 03:10:08 -0400 |
| commit | 903e90c31cf0319be9297529aa7b8daa1756cf63 (patch) | |
| tree | fe9e5c104b22d1cda6284fd96fce09339db5166e /src/radeon.h | |
| parent | 982c22f16c8eeee9be81779fbfe17d8d3f9b6897 (diff) | |
EXA/Xv: used cached bo tiling flags for accel setup on 6xx+
This avoids calling into the kernel for each bo in the accel
code. This is a follow on to:
cc7d1fa39da40a532fcdbe6c7924ca47a879e66a
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Diffstat (limited to 'src/radeon.h')
| -rw-r--r-- | src/radeon.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/radeon.h b/src/radeon.h index 9283c4dd..f655040a 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -1384,6 +1384,7 @@ void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size); #endif struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix); void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo); +uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix); #ifdef XF86DRI # ifdef USE_XAA |