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| author | Alex Deucher <alexdeucher@gmail.com> | 2008-08-14 14:49:45 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2008-08-14 14:49:45 -0400 |
| commit | 92ee21df344a989778e37369c7beb3904a00ead6 (patch) | |
| tree | 614c1163751f139fbb4e881889550dbffce8d0ca /src/radeon.h | |
| parent | 0d5e0347af4322713075193154b8a348de4a0b52 (diff) | |
PLL adjustments
Seems higher dotclocks prefer a higher FB div.
Someone with a lot of should try and find out where
the div sweet spots are for various dotclock ranges.
fixes bug 17125
Diffstat (limited to 'src/radeon.h')
| -rw-r--r-- | src/radeon.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/radeon.h b/src/radeon.h index 975e5d10..2348e7ce 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -250,7 +250,12 @@ typedef struct { #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) #define RADEON_PLL_USE_REF_DIV (1 << 2) #define RADEON_PLL_LEGACY (1 << 3) -#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) +#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) +#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) +#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) +#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) +#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) +#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) typedef struct { uint16_t reference_freq; |