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authorAlex Deucher <alex@botch2.(none)>2007-11-06 22:59:25 -0500
committerAlex Deucher <alex@botch2.(none)>2007-11-06 22:59:25 -0500
commit0d3e0735f710cb7b9505e4330997aa332f73c102 (patch)
tree002fb8271a042eb3151b9a6800f7dd87ebb94fe8 /src/radeon.h
parent0abfe3150ce3eed4db93ccc2975bd4622dfa54a7 (diff)
First round of avivo support
Diffstat (limited to 'src/radeon.h')
-rw-r--r--src/radeon.h111
1 files changed, 111 insertions, 0 deletions
diff --git a/src/radeon.h b/src/radeon.h
index 1d2235c2..766c1743 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -198,7 +198,110 @@ typedef struct {
CARD16 rr4_offset;
} RADEONBIOSInitTable;
+struct avivo_state
+{
+ CARD32 hdp_fb_location;
+ CARD32 mc_memory_map;
+ CARD32 vga_memory_base;
+ CARD32 vga_fb_start;
+
+ CARD32 vga1_cntl;
+ CARD32 vga2_cntl;
+
+ CARD32 pll1_post_div_cntl;
+ CARD32 pll1_post_div;
+ CARD32 pll1_post_div_mystery;
+ CARD32 pll1_post_mul;
+ CARD32 pll1_divider_cntl;
+ CARD32 pll1_divider;
+ CARD32 pll1_mystery0;
+ CARD32 pll1_mystery1;
+
+ CARD32 pll2_post_div_cntl;
+ CARD32 pll2_post_div;
+ CARD32 pll2_post_div_mystery;
+ CARD32 pll2_post_mul;
+ CARD32 pll2_divider_cntl;
+ CARD32 pll2_divider;
+ CARD32 pll2_mystery0;
+ CARD32 pll2_mystery1;
+
+ CARD32 crtc_pll_source;
+ CARD32 crtc1_h_total;
+ CARD32 crtc1_h_blank;
+ CARD32 crtc1_h_sync_wid;
+ CARD32 crtc1_h_sync_pol;
+ CARD32 crtc1_v_total;
+ CARD32 crtc1_v_blank;
+ CARD32 crtc1_v_sync_wid;
+ CARD32 crtc1_v_sync_pol;
+ CARD32 crtc1_cntl;
+ CARD32 crtc1_blank_status;
+ CARD32 crtc1_stereo_status;
+ CARD32 crtc1_scan_enable;
+ CARD32 crtc1_fb_format;
+ CARD32 crtc1_fb_location;
+ CARD32 crtc1_fb_end;
+ CARD32 crtc1_pitch;
+ CARD32 crtc1_x_length;
+ CARD32 crtc1_y_length;
+ CARD32 crtc1_fb_height;
+ CARD32 crtc1_offset_start;
+ CARD32 crtc1_offset_end;
+ CARD32 crtc1_expn_size;
+ CARD32 crtc1_expn_cntl;
+ CARD32 crtc1_6594;
+ CARD32 crtc1_659c;
+ CARD32 crtc1_65a4;
+ CARD32 crtc1_65a8;
+ CARD32 crtc1_65ac;
+ CARD32 crtc1_65b0;
+ CARD32 crtc1_65b8;
+ CARD32 crtc1_65bc;
+ CARD32 crtc1_65c0;
+ CARD32 crtc1_65c8;
+
+ CARD32 crtc2_h_total;
+ CARD32 crtc2_h_blank;
+ CARD32 crtc2_h_sync_wid;
+ CARD32 crtc2_h_sync_pol;
+ CARD32 crtc2_v_total;
+ CARD32 crtc2_v_blank;
+ CARD32 crtc2_v_sync_wid;
+ CARD32 crtc2_v_sync_pol;
+ CARD32 crtc2_cntl;
+ CARD32 crtc2_blank_status;
+ CARD32 crtc2_scan_enable;
+ CARD32 crtc2_fb_format;
+ CARD32 crtc2_fb_location;
+ CARD32 crtc2_fb_end;
+ CARD32 crtc2_pitch;
+ CARD32 crtc2_x_length;
+ CARD32 crtc2_y_length;
+
+ CARD32 dac1_cntl;
+ CARD32 dac1_force_output_cntl;
+ CARD32 dac1_powerdown;
+
+ CARD32 tmds1_cntl;
+ CARD32 tmds1_bit_depth_cntl;
+ CARD32 tmds1_data_sync;
+ CARD32 tmds1_transmitter_enable;
+ CARD32 tmds1_transmitter_cntl;
+
+ CARD32 dac2_cntl;
+ CARD32 dac2_force_output_cntl;
+ CARD32 dac2_powerdown;
+
+ CARD32 tmds2_cntl;
+ CARD32 tmds2_bit_depth_cntl;
+ CARD32 tmds2_data_sync;
+ CARD32 tmds2_transmitter_enable;
+ CARD32 tmds2_transmitter_cntl;
+};
+
typedef struct {
+ struct avivo_state avivo;
/* Common registers */
CARD32 ovr_clr;
CARD32 ovr_wid_left_right;
@@ -399,6 +502,9 @@ typedef enum {
CHIP_FAMILY_R420, /* R420/R423/M18 */
CHIP_FAMILY_RV410, /* RV410, M26 */
CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */
+ CHIP_FAMILY_RV515, /* rv515 */
+ CHIP_FAMILY_R520, /* r520 */
+ CHIP_FAMILY_R600, /* r60 */
CHIP_FAMILY_LAST
} RADEONChipFamily;
@@ -419,6 +525,8 @@ typedef enum {
(info->ChipFamily == CHIP_FAMILY_RV410) || \
(info->ChipFamily == CHIP_FAMILY_RS400))
+#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515))
+
/*
* Errata workarounds
*/
@@ -858,6 +966,9 @@ extern void RADEONEngineRestore(ScrnInfoPtr pScrn);
extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr);
extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data);
+extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr);
+extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data);
+
extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);