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authorAlex Deucher <alexdeucher@gmail.com>2008-08-14 14:49:45 -0400
committerAlex Deucher <alexdeucher@gmail.com>2008-08-14 14:49:45 -0400
commit92ee21df344a989778e37369c7beb3904a00ead6 (patch)
tree614c1163751f139fbb4e881889550dbffce8d0ca /src/radeon_accel.c
parent0d5e0347af4322713075193154b8a348de4a0b52 (diff)
PLL adjustments
Seems higher dotclocks prefer a higher FB div. Someone with a lot of should try and find out where the div sweet spots are for various dotclock ranges. fixes bug 17125
Diffstat (limited to 'src/radeon_accel.c')
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