diff options
| author | Alex Deucher <alex@botch2.com> | 2008-04-10 13:59:58 -0400 |
|---|---|---|
| committer | Alex Deucher <alex@botch2.com> | 2008-04-10 13:59:58 -0400 |
| commit | d79040906cd25bd494feb5901f465bbd050aa923 (patch) | |
| tree | 6b46da5442791a01915f0dffa099188e53be5b3d /src/radeon_accel.c | |
| parent | 0a96173cc38e506728d4c3f2dd383ba56e856578 (diff) | |
R3xx+: EXA/textured video fixes
- get pipe config based on GB_PIPE_SELECT where applicable
(adapted from a similar patch from Dave)
- only flush the dst cache after submitting vertices, freeing
the cache lines stalls the pipe
- no need to wait for 3D idle after submitting vertices
- fix PURGE_CACHE() and PURGE_ZCACHE() for r3xx+
- fix depth 16 with EXA composite
Diffstat (limited to 'src/radeon_accel.c')
| -rw-r--r-- | src/radeon_accel.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/radeon_accel.c b/src/radeon_accel.c index 015d1763..67dae7cb 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -400,6 +400,33 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) info->aux_sc_cntl = 0x00000000; #endif + if ((info->ChipFamily == CHIP_FAMILY_RV410) || + (info->ChipFamily == CHIP_FAMILY_R420) || + (info->ChipFamily == CHIP_FAMILY_RS690) || + (info->ChipFamily == CHIP_FAMILY_RS740) || + (info->ChipFamily == CHIP_FAMILY_RS400) || + IS_R500_3D) { + uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); + if (info->num_gb_pipes == 0) { + info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "%s: num pipes is %d\n", __FUNCTION__, info->num_gb_pipes); + } + if (IS_R500_3D) + OUTPLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); + } else { + if (info->num_gb_pipes == 0) { + if ((info->ChipFamily == CHIP_FAMILY_R300) || + (info->ChipFamily == CHIP_FAMILY_R350)) { + /* R3xx chips */ + info->num_gb_pipes = 2; + } else { + /* RV3xx chips */ + info->num_gb_pipes = 1; + } + } + } + RADEONEngineRestore(pScrn); } |