diff options
| author | Roland Scheidegger <rscheidegger_lists@hispeed.ch> | 2005-01-26 18:23:41 +0000 |
|---|---|---|
| committer | Roland Scheidegger <rscheidegger_lists@hispeed.ch> | 2005-01-26 18:23:41 +0000 |
| commit | a2b123f7672ea678290798786ecb408a86d8c683 (patch) | |
| tree | b3ee76a2664b7156875b5abb4891d0499e56994a /src/radeon_accel.c | |
| parent | e0df1e41724cd009fe7c833d2f9555f5d87e3202 (diff) | |
(Stephane Marchesin, me) Add support for color (framebuffer) tiling.
Convert all XAA accel code to use explicit dst and src offset pitch
control to make it work. Use the new drm surface ioctls to set up the
tiled surfaces (if dri is enabled).
Diffstat (limited to 'src/radeon_accel.c')
| -rw-r--r-- | src/radeon_accel.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/radeon_accel.c b/src/radeon_accel.c index d11c7c8c..e2f479d3 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -303,9 +303,9 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) pitch64 = ((pScrn->displayWidth * (pScrn->bitsPerPixel / 8) + 0x3f)) >> 6; - RADEONWaitForFifo(pScrn, 1); - OUTREG(RADEON_DEFAULT_OFFSET, ((info->fbLocation >> 10) - | (pitch64 << 22))); +/* RADEONWaitForFifo(pScrn, 2); + OUTREG(RADEON_DST_PITCH_OFFSET, info->dst_pitch_offset); + OUTREG(RADEON_SRC_PITCH_OFFSET, info->dst_pitch_offset);*/ RADEONWaitForFifo(pScrn, 1); #if X_BYTE_ORDER == X_BIG_ENDIAN @@ -376,7 +376,8 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) info->dp_gui_master_cntl = ((info->datatype << RADEON_GMC_DST_DATATYPE_SHIFT) - | RADEON_GMC_CLR_CMP_CNTL_DIS); + | RADEON_GMC_CLR_CMP_CNTL_DIS + | RADEON_GMC_DST_PITCH_OFFSET_CNTL); #ifdef XF86DRI info->sc_left = 0x00000000; |