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authorAlex Deucher <alex@botch2.com>2008-06-11 14:29:36 -0400
committerAlex Deucher <alex@botch2.com>2008-06-11 14:29:36 -0400
commitada41723fdc8cbeeda12bb4ae2d16e8d1ba215de (patch)
tree3136e202049a7aaeefdd5c89a346b8712180c2ef /src/radeon_accel.c
parent3d70c398afa0831387af81559453b77c218a54f9 (diff)
R3xx: use DSTCACHE_CTLSTAT rather than RB2D_DSTCACHE_CTLSTAT
According to the hw guys, you should use DSTCACHE_CTLSTAT to flush the 2D dst cache rather than RB2D_DSTCACHE_CTLSTAT.
Diffstat (limited to 'src/radeon_accel.c')
-rw-r--r--src/radeon_accel.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 4ce0da62..5897c7e6 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -172,17 +172,17 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn)
(unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
}
} else {
- OUTREGP(R300_RB2D_DSTCACHE_CTLSTAT,
+ OUTREGP(R300_DSTCACHE_CTLSTAT,
R300_RB2D_DC_FLUSH_ALL,
~R300_RB2D_DC_FLUSH_ALL);
for (i = 0; i < RADEON_TIMEOUT; i++) {
- if (!(INREG(R300_RB2D_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY))
+ if (!(INREG(R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY))
break;
}
if (i == RADEON_TIMEOUT) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"DC flush timeout: %x\n",
- (unsigned int)INREG(R300_RB2D_DSTCACHE_CTLSTAT));
+ (unsigned int)INREG(R300_DSTCACHE_CTLSTAT));
}
}
}