diff options
| author | Alex Deucher <agd5f@yahoo.com> | 2004-07-26 23:14:37 +0000 |
|---|---|---|
| committer | Alex Deucher <agd5f@yahoo.com> | 2004-07-26 23:14:37 +0000 |
| commit | 26029dc9378bbd95835d397402bfc9e6b4f1a478 (patch) | |
| tree | 3b76ba895c223a848daeba0752766820242c41eb /src/radeon_accel.c | |
| parent | 9f251b16e702da486f824307e72a6f80c6987b5d (diff) | |
- Add Radeon DynamicClocks option
- Add small fixes and clean ups from ati's last code drop (typo_fixes,
remove_fudge, laptop, xvfix)
- fix possible segfault in mga_dri.c (Ryan Underwood)
- Add Xv support to pre-nm2160 neomagic chipsets
Diffstat (limited to 'src/radeon_accel.c')
| -rw-r--r-- | src/radeon_accel.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/radeon_accel.c b/src/radeon_accel.c index 6bebd6c1..c91c5cc8 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -175,6 +175,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); if (info->R300CGWorkaround) R300CGWorkaround(pScrn); +#if 0 /* taken care of by new PM code */ /* Some ASICs have bugs with dynamic-on feature, which are * ASIC-version dependent, so we force all blocks on for now */ @@ -191,8 +192,11 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) OUTPLL(RADEON_SCLK_MORE_CNTL, tmp | RADEON_SCLK_MORE_FORCEON); } } +#endif /* new PM code */ mclk_cntl = INPLL(pScrn, RADEON_MCLK_CNTL); + +#if 0 /* handled by new PM code */ OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl | RADEON_FORCEON_MCLKA | RADEON_FORCEON_MCLKB | @@ -200,6 +204,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC | RADEON_FORCEON_AIC)); +#endif /* new PM code */ /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some * unexpected behaviour on some machines. Here we use |