diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2009-04-30 19:13:09 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2009-04-30 19:13:09 -0400 |
| commit | de17d36c1f710305870e3c636cae3f742f1cb6d6 (patch) | |
| tree | 7c2dda67182fb61eacd80a09db9e7348079d84f8 /src/radeon_atombios.c | |
| parent | 7d9f643ae3d07e51e644a5979ca90bc2c102bc89 (diff) | |
AVIVO: first pass at display watermark setup
This helps with flickering and blanking when
there is contention for MC bandwidth.
Diffstat (limited to 'src/radeon_atombios.c')
| -rw-r--r-- | src/radeon_atombios.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c index 389b1453..110a7ccc 100644 --- a/src/radeon_atombios.c +++ b/src/radeon_atombios.c @@ -2027,6 +2027,35 @@ RADEONGetATOMLVDSInfo(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds) native_mode->VBlank, native_mode->VOverPlus, native_mode->VSyncWidth); } +void +RADEONATOMGetIGPInfo(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + atomDataTablesPtr atomDataPtr; + unsigned short size; + uint8_t crev, frev; + + atomDataPtr = info->atomBIOS->atomDataPtr; + + if (!rhdAtomGetTableRevisionAndSize((ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->IntegratedSystemInfo.base), &frev, &crev, &size)) + return; + + switch (crev) { + case 1: + info->igp_sideport_mclk = atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo->ulBootUpMemoryClock / 100.0; + info->igp_system_mclk = le16_to_cpu(atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo->usK8MemoryClock); + info->igp_ht_link_clk = le16_to_cpu(atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo->usFSBClock); + info->igp_ht_link_width = atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo->ucHTLinkWidth; + break; + case 2: + info->igp_sideport_mclk = atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2->ulBootUpSidePortClock / 100.0; + info->igp_system_mclk = atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2->ulBootUpUMAClock / 100.0; + info->igp_ht_link_clk = atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2->ulHTLinkFreq / 100.0; + info->igp_ht_link_width = le16_to_cpu(atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2->usMinHTLinkWidth); + break; + } +} + Bool RADEONGetATOMTVInfo(xf86OutputPtr output) { |